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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTestSuite
/
opt
/
opt_share_add_sub.v
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module
opt_share_test
(
input
[
15
:
0
]
a
,
input
[
15
:
0
]
b
,
input sel
,
output
[
15
:
0
]
res
,
);
assign res
=
{
sel
?
a
+
b
:
a
-
b
};
endmodule