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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
architecture
/
synth_efinix_fulladder
/
top.v
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module
top
(
input
[
3
:
0
]
x
,
input
[
3
:
0
]
y
,
input
[
3
:
0
]
cin
,
output
[
4
:
0
]
A
,
output
[
4
:
0
]
cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`
else
assign
{
cout
,
A
}
=
cin
-
y
*
x
;
`endif
endmodule