blob: 0e0ba101f5395c4656cccf281497230a28c68d16 [file] [log] [blame]
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -module_name top aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v