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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
pmux2shiftx_2
/
top.v
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module
top
(
input
[
7
:
0
]
i
,
output o
);
always
@*
case
(
i
[
6
:
3
])
4
:
o
<=
i
[
0
];
3
:
o
<=
i
[
2
];
7
:
o
<=
i
[
3
];
default
:
o
<=
1
'b0;
endcase
endmodule
