SVIncCompil/Testcases/YosysTests/regression/issue_00088/testbench.v

module testbench;
    reg clk;

    initial begin
       // $dumpfile("testbench.vcd");
       // $dumpvars(0, testbench);

        #0 clk = 0;
        repeat (10000) begin
            #5 clk = 1;
            #5 clk = 0;
        end

        $display("OKAY");
    end
	wire c;

    top uut (
        .b (clk ),
        .c (c)
    );

endmodule