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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00091
/
top.v
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module
top
(
A
,
clk
,
rst
);
input clk
,
rst
;
output A
;
parameter GPIO_COUNT
=
16
;
initial
begin
if
(
GPIO_COUNT
<
0
||
GPIO_COUNT
>
16
)
begin
$display
(
"Parameter Error: GPIO_COUNT must be in range 0..16"
);
$finish
;
end
end
endmodule