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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00096
/
top.v
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module
top
(
b
);
integer
inout b
;
reg c
;
assign
&
0
=
0
;
assign
0
=
0
;
always
i
=
0
;
always
if
(
8
)
b
=
_
;
always
if
(
8
)
b
=
M
&
0
;
endmodule
