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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00173
/
top.v
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module
top
(
input ai
,
bi
,
ci
,
output reg ao
,
bo
,
co
);
always@
*
begin
ao
=
ai
;
bo
=
bi
;
co
=
ci
;
{
co
,
co
,
bo
,
ao
}
=
{
ai
,
bi
,
ai
,
ci
};
// Error: multiple assignment to 'co' with blocking assignment
end
endmodule