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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00182
/
testbench.v
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module
testbench
;
reg clk
;
initial
begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat
(
10000
)
begin
#5 clk = 1;
#5 clk = 0;
end
$display
(
"OKAY"
);
end
endmodule