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foss-fpga-tools
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third_party
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Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00349
/
top.v
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module
top
(
input wire x
,
input wire y
,
output reg z
);
always
@*
z
<=
x
~&
y
;
endmodule
