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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00361
/
top.v
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module
top
(
input
[
63
:
0
]
A
,
B
,
C
,
D
,
input
[
127
:
0
]
E
,
F
,
output reg
[
127
:
0
]
X
,
Y
);
integer i
;
always
@*
begin
X
=
A
*
B
+
E
;
Y
=
F
;
for
(
i
=
0
;
i
<
64
;
i
=
i
+
1
)
Y
=
Y
+
C
[
i
]*
D
[
i
];
end
endmodule