SVIncCompil/Testcases/YosysTests/regression/issue_00372/top.v - third_party/Surelog - Git at Google

 module top(clk,d,q);
 input clk,d;
 output reg q;

 always @(posedge clk)
 if (!1'h1)
   q <= 0;
 else
   q <= d;

 endmodule
	module top(clk,d,q);
	input clk,d;
	output reg q;

	always @(posedge clk)
	if (!1'h1)
	q <= 0;
	else
	q <= d;

	endmodule