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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00432
/
top.v
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module
top
(
a
,
b
,
c
);
input
[
7
:
0
]
a
;
input
[
7
:
0
]
b
;
output
[
7
:
0
]
c
;
assign c
=
a
[
$signed
(
b
)
+:
8
];
endmodule
