Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00635
/
top.v
blob: bd8b0cc3444f113e77664291851c3b9303e6d8fb [
file
] [
log
] [
blame
]
module
top
(
input clk
,
input rstn
,
input en
,
input
[
XLEN
-
1
:
0
]
d
,
output
[
XLEN
-
1
:
0
]
q
);
parameter XLEN
=
4
;