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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00675
/
top.v
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module
graphtest
(
A
,
Y
,
Z
);
input
[
3
:
0
]
A
;
output
[
2
:
0
]
Y
;
output
[
1
:
0
]
Z
;
assign Y
=
{
A
[
2
:
0
]
&
3
'h2 };
assign Z = A[2:1];
endmodule