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foss-fpga-tools
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third_party
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Surelog
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356a4bf2123fc606ca19fbed9b9c535f149fdec5
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.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00737
/
top.v
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module
top
(
input wire iw
,
output wire ow
);
localparam j
=
2
;
(*
A
=
2
*)
(*
B
=
j
+
1
*)
SB_LUT4
#(
.
LUT_INIT
(
16
'h0001)
) test_I (
.I0(iw),
.I1(),
.I2(),
.I3(),
.O(ow)
);
endmodule