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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00809
/
top.v
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module
top
(
C
,
O
,
A
,
B
);
input
[
3
:
0
]
A
;
input
[
3
:
0
]
B
;
output
[
3
:
0
]
O
;
output C
;
assign
{
C
,
O
}
=
A
+
B
;
endmodule
