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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_00954
/
top.v
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module
lutbug
(
addr
,
out
);
input
[
7
:
0
]
addr
;
output
[
3
:
0
]
out
;
assign
out
=
addr
[
7
:
4
]
*
addr
[
3
:
0
];
endmodule
