SVIncCompil/Testcases/YosysTests/regression/issue_01016/top.v - third_party/Surelog - Git at Google

 module mux_x(clk, in, en, out);
    input clk, in, en;
    output out;

    assign out = en ? in : 1'bx;

 endmodule // latchx
	module mux_x(clk, in, en, out);
	input clk, in, en;
	output out;

	assign out = en ? in : 1'bx;

	endmodule // latchx