SVIncCompil/Testcases/YosysTests/regression/issue_01065/top.v - third_party/Surelog - Git at Google

 module top(input clk);
 wire ce = 1'b1;
 reg q = 1'b0;
 always @(posedge clk)
     if (ce) q <= 1'b0;

 (* keep *)
 unknown_module u(.i(q));
 endmodule
	module top(input clk);
	wire ce = 1'b1;
	reg q = 1'b0;
	always @(posedge clk)
	if (ce) q <= 1'b0;

	(* keep *)
	unknown_module u(.i(q));
	endmodule