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foss-fpga-tools
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third_party
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Surelog
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356a4bf2123fc606ca19fbed9b9c535f149fdec5
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.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01070
/
top.v
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module
top
(
input clk
,
d
,
output reg q
);
wire ce
=
1
'b1;
always @(negedge clk)
if (ce) q <= d;
endmodule
