SVIncCompil/Testcases/YosysTests/regression/issue_01206/top.il - third_party/Surelog - Git at Google

 autoidx 1
 attribute \top 1
 module \top
   wire width 1073741824 $1
   wire width 1073741824 $2
   process $group_0
     sync init
   end
   connect $1 $2
 end
	autoidx 1
	attribute \top 1
	module \top
	wire width 1073741824 $1
	wire width 1073741824 $2
	process $group_0
	sync init
	end
	connect $1 $2
	end