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foss-fpga-tools
/
third_party
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Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
regression
/
issue_01273
/
top.v
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module
top
(
input
[
5
:
0
]
S
,
input
[
63
:
0
]
D
,
output M256
);
assign M256
=
D
[
S
];
endmodule
