Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
simple
/
scripts
/
extract_wire_attr.ys
blob: a39654a59c3aa6bba4f219e7084c1ca27ed11ec9 [
file
] [
log
] [
blame
]
read_verilog
../
top
.
v
extract
-
map
../
top
.
v
-
wire_attr attr
design
-
reset
read_verilog
../
top
.
v
proc
write_verilog synth
.
v