blob: 8e43d623e70bc169aca6d8bf64cf37d7ff5f0f0e [file] [log] [blame]
read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40 -assert
tee -o result.log dump
write_verilog synth.v