blob: 112362d824dfb31bde2b326d4e04b9bd1ae88392 [file] [log] [blame]
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol neg
design -reset
read_verilog ../top.v
write_verilog synth.v