blob: 1f6c58e6b980d4229c5704747880bdeb55fdd530 [file] [log] [blame]
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -match -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v