blob: b39ae1ac16988e67c11b5d4f56778b0e34bb7e86 [file] [log] [blame]
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -match foobar -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v