| <html><head><title>UVM 1.2 Class Reference</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script></head><body class="FramedContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!-- |
| if (browserType) {document.write("<div class=" + browserType + ">");if (browserVer) {document.write("<div class=" + browserVer + ">"); }}// --></script> |
| |
| <!-- Generated by Natural Docs, version Development Release 01-12-2008 (1.35 base) --> |
| <!-- http://www.naturaldocs.org --> |
| |
| <!-- saved from url=(0026)http://www.naturaldocs.org --> |
| |
| |
| |
| |
| |
| |
| |
| |
| <!--TOP - START OF CONTENT--> |
| <div id=Content> |
| |
| |
| <!--CONTENT index=0 --> |
| <div class="CSection"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="UVM_1.2_Class_Reference" href="../../src/overviews/intro.txt">UVM 1.<span class=HB> </span>2 Class Reference</a></h1><div class=CBody><p>The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.</p><p>This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.</p><p>We divide the UVM classes and utilities into categories pertaining to their role or function. A more detailed overview of each category-- and the classes comprising them-- can be found in the menu at left.</p><table border=0 cellspacing=0 cellpadding=0 class=CDescriptionList><tr><td class=CDLEntry>Globals</td><td class=CDLDescription>This category defines a small list of types, variables, functions, and tasks defined in the <i>uvm_pkg</i> scope. These items are accessible from any scope that imports the <i>uvm_pkg</i>. See <a href="../base/uvm_object_globals-svh.html#Types_and_Enumerations" class=LSection >Types and Enumerations</a> and <a href="../tlm2/uvm_tlm2_generic_payload-svh.html#Globals" class=LGroup id=link1 onMouseOver="ShowTip(event, 'tt1', 'link1')" onMouseOut="HideTip('tt1')">Globals</a> for details.</td></tr><tr><td class=CDLEntry>Base</td><td class=CDLDescription>This basic building blocks for all environments are components, which do the actual work, transactions, which convey information between components, and ports, which provide the interfaces used to convey transactions. The UVM’s core <i>base</i> classes provide these building blocks. See <a href="base-txt.html#Core_Base_Classes" class=LSection id=link2 onMouseOver="ShowTip(event, 'tt2', 'link2')" onMouseOut="HideTip('tt2')">Core Base Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Reporting</td><td class=CDLDescription>The <i>reporting</i> classes provide a facility for issuing reports (messages) with consistent formatting and configurable side effects, such as logging to a file or exiting simulation. Users can also filter out reports based on their verbosity , unique ID, or severity. See <a href="reporting-txt.html#Reporting_Classes" class=LGroup id=link3 onMouseOver="ShowTip(event, 'tt3', 'link3')" onMouseOut="HideTip('tt3')">Reporting Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Factory</td><td class=CDLDescription>As the name implies, the UVM factory is used to manufacture (create) UVM objects and components. Users can configure the factory to produce an object of a given type on a global or instance basis. Use of the factory allows dynamically configurable component hierarchies and object substitutions without having to modify their code and without breaking encapsulation. See <a href="factory-txt.html#Factory_Classes" class=LSection id=link4 onMouseOver="ShowTip(event, 'tt4', 'link4')" onMouseOut="HideTip('tt4')">Factory Classes</a> for details.</td></tr><tr><td class=CDLEntry>Phasing</td><td class=CDLDescription>This sections describes the phasing capability providing by UVM. The details can be found in <a href="phasing-txt.html#Phasing_Overview" class=LSection id=link5 onMouseOver="ShowTip(event, 'tt5', 'link5')" onMouseOut="HideTip('tt5')">Phasing Overview</a>.</td></tr><tr><td class=CDLEntry>Configuration and Resources</td><td class=CDLDescription>The <a href="config_and_res-txt.html#Configuration_and_Resource_Classes" class=LSection id=link6 onMouseOver="ShowTip(event, 'tt6', 'link6')" onMouseOut="HideTip('tt6')">Configuration and Resource Classes</a> are a set of classes which provide a configuration database. The configuration database is used to store and retrieve both configuration time and run time properties.</td></tr><tr><td class=CDLEntry>Synchronization</td><td class=CDLDescription>The UVM provides event and barrier synchronization classes for process synchronization. See <a href="synchro-txt.html#Synchronization_Classes" class=LSection >Synchronization Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Containers</td><td class=CDLDescription>The <a href="containers-txt.html#Container_Classes" class=LSection id=link7 onMouseOver="ShowTip(event, 'tt7', 'link7')" onMouseOut="HideTip('tt7')">Container Classes</a> are type parameterized data structures which provide queue and pool services. The class based queue and pool types allow for efficient sharing of the data structures compared with their SystemVerilog built-in counterparts.</td></tr><tr><td class=CDLEntry>Policies</td><td class=CDLDescription>Each of UVM’s policy classes performs a specific task for <a href="../base/uvm_object-svh.html#uvm_object" class=LClass id=link8 onMouseOver="ShowTip(event, 'tt8', 'link8')" onMouseOut="HideTip('tt8')">uvm_object</a>-based objects: printing, comparing, recording, packing, and unpacking. They are implemented separately from <i>uvm_object</i> so that users can plug in different ways to print, compare, etc. without modifying the object class being operated on. The user can simply apply a different printer or compare “policy” to change how an object is printed or compared. See <a href="policies-txt.html#Policy_Classes" class=LSection id=link9 onMouseOver="ShowTip(event, 'tt9', 'link9')" onMouseOut="HideTip('tt9')">Policy Classes</a> for more information.</td></tr><tr><td class=CDLEntry>TLM</td><td class=CDLDescription>The UVM TLM library defines several abstract, transaction-level interfaces and the ports and exports that facilitate their use. Each TLM interface consists of one or more methods used to transport data, typically whole transactions (objects) at a time. Component designs that use TLM ports and exports to communicate are inherently more reusable, interoperable, and modular. See <a href="tlm_ifs_and_ports-txt.html#TLM_Interfaces" class=LSection id=link10 onMouseOver="ShowTip(event, 'tt10', 'link10')" onMouseOut="HideTip('tt10')">TLM Interfaces</a> for details.</td></tr><tr><td class=CDLEntry>Components</td><td class=CDLDescription>Components form the foundation of the UVM. They encapsulate behavior of drivers, scoreboards, and other objects in a testbench. The UVM library provides a set of predefined component types, all derived directly or indirectly from <a href="../base/uvm_component-svh.html#uvm_component" class=LClass id=link11 onMouseOver="ShowTip(event, 'tt11', 'link11')" onMouseOut="HideTip('tt11')">uvm_component</a>. See <a href="components-txt.html#Predefined_Component_Classes" class=LGroup id=link12 onMouseOver="ShowTip(event, 'tt12', 'link12')" onMouseOut="HideTip('tt12')">Predefined Component Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Sequencers</td><td class=CDLDescription>The sequencer serves as an arbiter for controlling transaction flow from multiple stimulus generators. More specifically, the sequencer controls the flow of <a href="../seq/uvm_sequence_item-svh.html#uvm_sequence_item" class=LClass id=link13 onMouseOver="ShowTip(event, 'tt13', 'link13')" onMouseOut="HideTip('tt13')">uvm_sequence_item</a>-based transactions generated by one or more <a href="../seq/uvm_sequence-svh.html#uvm_sequence#(REQ,RSP)" class=LClass id=link14 onMouseOver="ShowTip(event, 'tt14', 'link14')" onMouseOut="HideTip('tt14')">uvm_sequence #(REQ,RSP)</a>-based sequences. See <a href="sequencers-txt.html#Sequencer_Classes" class=LSection id=link15 onMouseOver="ShowTip(event, 'tt15', 'link15')" onMouseOut="HideTip('tt15')">Sequencer Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Sequences</td><td class=CDLDescription>Sequences encapsulate user-defined procedures that generate multiple <a href="../seq/uvm_sequence_item-svh.html#uvm_sequence_item" class=LClass id=link16 onMouseOver="ShowTip(event, 'tt13', 'link16')" onMouseOut="HideTip('tt13')">uvm_sequence_item</a>-based transactions. Such sequences can be reused, extended, randomized, and combined sequentially and hierarchically in interesting ways to produce realistic stimulus to your DUT. See <a href="sequences-txt.html#Sequence_Classes" class=LSection id=link17 onMouseOver="ShowTip(event, 'tt16', 'link17')" onMouseOut="HideTip('tt16')">Sequence Classes</a> for more information.</td></tr><tr><td class=CDLEntry>Macros</td><td class=CDLDescription>The UVM provides several macros to help increase user productivity. See the set of macro categories in the main menu for a complete list of macros for Reporting, Components, Objects, Sequences, Callbacks, TLM and Registers.</td></tr><tr><td class=CDLEntry>Register Layer</td><td class=CDLDescription>The Register abstraction classes, when properly extended, abstract the read/write operations to registers and memories in a design-under-verification. See <a href="registers-txt.html#Register_Layer" class=LSection id=link18 onMouseOver="ShowTip(event, 'tt17', 'link18')" onMouseOut="HideTip('tt17')">Register Layer</a> for more information.</td></tr><tr><td class=CDLEntry>Command Line Processor</td><td class=CDLDescription>The command line processor provides a general interface to the command line arguments that were provided for the given simulation. The capabilities are detailed in the <a href="../base/uvm_cmdline_processor-svh.html#uvm_cmdline_processor" class=LClass id=link19 onMouseOver="ShowTip(event, 'tt18', 'link19')" onMouseOut="HideTip('tt18')">uvm_cmdline_processor</a> section.</td></tr></table> |
| |
| <!--START_ND_SUMMARY index=0--> |
| <div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable> |
| <!-- index=0 --> |
| |
| <tr class="SMain"><td colspan=2 class=SEntry><a href="#UVM_1.2_Class_Reference" >UVM 1.<span class=HB> </span>2 Class Reference</a></td></tr> |
| <tr class=SMain><td colspan=2 class=SWideDescription>The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.</td></tr></table></div></div><!--END_ND_SUMMARY--> |
| </div></div></div> |
| |
| </div><!--Content--> |
| |
| |
| |
| <!--START_ND_TOOLTIPS--> |
| <div class=CToolTip id="tt1"><div class=CGroup>Defines, Constants, enums.</div></div><div class=CToolTip id="tt2"><div class=CSection>The UVM library defines a set of base classes and utilities that facilitate the design of modular, scalable, reusable verification environments.</div></div><div class=CToolTip id="tt3"><div class=CGroup>The reporting classes provide a facility for issuing reports with consistent formatting. </div></div><div class=CToolTip id="tt4"><div class=CSection>As the name implies, the uvm_factory is used to manufacture (create) UVM objects and components. </div></div><div class=CToolTip id="tt5"><div class=CSection>UVM implements an automated mechanism for phasing the execution of the various components in a testbench.</div></div><div class=CToolTip id="tt6"><div class=CSection>The configuration and resources classes provide access to a centralized database where type specific information can be stored and received. </div></div><div class=CToolTip id="tt7"><div class=CSection>The container classes are type parameterized data structures. </div></div><div class=CToolTip id="tt8"><div class=CClass> |
| <blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>virtual class uvm_object extends uvm_void |
| </td></tr></table></blockquote>The uvm_object class is the base class for all UVM data and hierarchical classes. </div></div><div class=CToolTip id="tt9"><div class=CSection>Each of UVM’s policy classes perform a specific task for uvm_object-based objects: printing, comparing, recording, packing, and unpacking. </div></div><div class=CToolTip id="tt10"><div class=CSection>The UVM TLM library defines several abstract, transaction-level interfaces and the ports and exports that facilitate their use. </div></div><div class=CToolTip id="tt11"><div class=CClass> |
| <blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>virtual class uvm_component extends uvm_report_object |
| </td></tr></table></blockquote>The uvm_component class is the root base class for UVM components. </div></div><div class=CToolTip id="tt12"><div class=CGroup>Components form the foundation of the UVM. </div></div><div class=CToolTip id="tt13"><div class=CClass> |
| <blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>class uvm_sequence_item extends uvm_transaction |
| </td></tr></table></blockquote>The base class for user-defined sequence items and also the base class for the uvm_sequence class. </div></div><div class=CToolTip id="tt14"><div class=CClass> |
| <blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype> |
| <tr><td><table border=0 cellspacing=0 cellpadding=0><tr> |
| <td class=PBeforeParameters colspan=5>virtual class uvm_sequence #(</td> </tr><tr><td> </td> <td class=PType nowrap>type </td> |
| <td class=PParameter nowrap>REQ</td> |
| <td class=PDefaultValuePrefix> = </td> |
| <td class=PDefaultValue width=100%> uvm_sequence_item,</td> |
| </tr><tr><td> </td> <td class=PType nowrap>type </td> |
| <td class=PParameter nowrap>RSP</td> |
| <td class=PDefaultValuePrefix> = </td> |
| <td class=PDefaultValue width=100%> REQ</td> |
| </tr> |
| <tr> |
| <td class=PAfterParameters colspan=5>) extends uvm_sequence_base</td></tr> |
| </table></td></tr> |
| </table></blockquote> |
| The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.</div></div><div class=CToolTip id="tt15"><div class=CSection>The sequencer serves as an arbiter for controlling transaction flow from multiple stimulus generators. </div></div><div class=CToolTip id="tt16"><div class=CSection>Sequences encapsulate user-defined procedures that generate multiple uvm_sequence_item-based transactions. </div></div><div class=CToolTip id="tt17"><div class=CSection>The UVM register layer defines several base classes that, when properly extended, abstract the read/write operations to registers and memories in a design-under-verification.</div></div><div class=CToolTip id="tt18"><div class=CClass> |
| <blockquote><table border=0 cellspacing=0 cellpadding=0 class=Prototype><tr><td>class uvm_cmdline_processor extends uvm_report_object |
| </td></tr></table></blockquote>This class provides an interface to the command line arguments that were provided for the given simulation. </div></div><!--END_ND_TOOLTIPS--> |
| |
| <script language=JavaScript><!-- |
| if (browserType) {if (browserVer) {document.write("</div>"); }document.write("</div>");}// --></script></body></html> |
