| <html><head><title>Macros and Defines</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script></head><body class="FramedContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!-- |
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| <div class="CSection"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="Macros_and_Defines" href="../../src/overviews/macros.txt">Macros and Defines</a></h1><div class=CBody><p>UVM includes some macros to allow the user to specify intent without the need to specify multiple types of SystemVerilog constructs. These macros assist with reporting, object behavior (interaction with the factory and field usage in comparing/copying/etc), sequence specification, and TLM connection.</p><p>UVM also includes some defines to specify sizing in the register space and to determine version of the UVM standard and/or implementation.</p> |
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| <div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable> |
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| <tr class="SMain"><td colspan=2 class=SEntry><a href="#Macros_and_Defines" >Macros and Defines</a></td></tr> |
| <tr class=SMain><td colspan=2 class=SWideDescription>UVM includes some macros to allow the user to specify intent without the need to specify multiple types of SystemVerilog constructs. </td></tr></table></div></div><!--END_ND_SUMMARY--> |
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