| <html><head><title>Register Layer</title><link rel="stylesheet" type="text/css" href="../../styles/main.css"><script language=JavaScript src="../../javascript/main.js"></script></head><body class="FramedContentPage" onLoad="NDOnLoad()"><script language=JavaScript><!-- |
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| <div class="CSection"><div class=CTopic id=MainTopic><h1 class=CTitle><a name="Register_Layer" href="../../src/overviews/registers.txt">Register Layer</a></h1><div class=CBody><p>The UVM register layer defines several base classes that, when properly extended, abstract the read/write operations to registers and memories in a design-under-verification.</p><p>A register model is typically composed of a hierarchy of blocks that usually map to the design hierarchy. Blocks contain registers, register files and memories.</p><p>The UVM register layer classes are not usable as-is. They only provide generic and introspection capabilities. They must be specialized via extensions to provide an abstract view that corresponds to the actual registers and memories in a design. Due to the large number of registers in a design and the numerous small details involved in properly configuring the UVM register layer classes, this specialization is normally done by a model generator. Model generators work from a specification of the registers and memories in a design and are thus able to provide an up-to-date, correct-by-construction register model. Model generators are outside the scope of the UVM library.</p><p>The class diagram of a register layer model is shown below.</p><img src="../../images/uvm_ref_reg_class_map.gif" width="670" height="499"> |
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| <div class=Summary><div class=STitle>Summary</div><div class=SBorder><table border=0 cellspacing=0 cellpadding=0 class=STable> |
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| <tr class="SMain"><td colspan=2 class=SEntry><a href="#Register_Layer" >Register Layer</a></td></tr> |
| <tr class=SMain><td colspan=2 class=SWideDescription>The UVM register layer defines several base classes that, when properly extended, abstract the read/write operations to registers and memories in a design-under-verification.</td></tr></table></div></div><!--END_ND_SUMMARY--> |
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