| [INFO :CM0023] Creating log file ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/surelog.log. |
| |
| [INFO :CM0020] Separate compilation-unit mode is on. |
| |
| [WARNI:CM0007] Library path "blah" does not exist. |
| |
| [INFO :PP0122] Preprocessing source file "builtin.sv". |
| |
| [INFO :PP0122] Preprocessing source file "top.v". |
| |
| [INFO :PP0123] Preprocessing include file "my_incl.vh". |
| |
| [INFO :PP0123] Preprocessing include file "foo/bar.vh". |
| |
| [INFO :PP0123] Preprocessing include file "mode.vh". |
| |
| [ERROR:PP0109] mode.vh:36 Macro instantiation omits argument 2 (y) for "D", |
| mode.vh:25 No default value for argument 2 (y) in macro definition. |
| |
| [ERROR:PP0109] mode.vh:38 Macro instantiation omits argument 1 (x) for "D", |
| mode.vh:25 No default value for argument 1 (x) in macro definition. |
| |
| [ERROR:PP0109] mode.vh:38 Macro instantiation omits argument 2 (y) for "D", |
| mode.vh:25 No default value for argument 2 (y) in macro definition. |
| |
| [ERROR:PP0107] mode.vh:40 Too many arguments (3) for macro "D", |
| mode.vh:25 macro definition takes 2. |
| |
| [NOTE :PP0105] mode.vh:42 Multiply defined macro "MACRO1", |
| fake.sv:215 previous definition. |
| |
| [ERROR:PP0109] mode.vh:49 Macro instantiation omits argument 3 (c) for "MACRO1", |
| mode.vh:42 No default value for argument 3 (c) in macro definition. |
| |
| [ERROR:PP0110] mode.vh:62 Macro instantiation omits parenthesis for "MACRO3", |
| mode.vh:57 macro definition has arguments. |
| |
| [NOTE :PP0105] top.v:10 Multiply defined macro "single", |
| fake.sv:213 previous definition. |
| |
| [WARNI:PP0103] top.v:15 Undefining an unknown macro "multipl". |
| |
| [INFO :PP0123] Preprocessing include file "wire.vh". |
| |
| [ERROR:PP0120] mode.vh:15 Illegal directive in design element "`timescale", |
| top.v:22 macro instance. |
| |
| [ERROR:PP0120] top.v:39 Illegal directive in design element "`resetall". |
| |
| [ERROR:PP0115] top.v:44 Recursive macro definition for "BOTTOM", |
| top.v:45 macro used in macro "TOP". |
| |
| [ERROR:PP0102] top.v:44 Unknown macro "TOP". |
| |
| [INFO :PP0122] Preprocessing source file "top_1.v". |
| |
| [SYNTX:PP0106] top_1.v:13 Syntax error: missing Simple_identifier at '\n', |
| `default_nettype |
| ^-- top_1.v:13 col:17. |
| |
| [WARNI:PP0103] top_1.v:15 Undefining an unknown macro "multipl". |
| |
| [ERROR:PP0120] mode.vh:15 Illegal directive in design element "`timescale", |
| top_1.v:22 macro instance. |
| |
| [WARNI:PP0113] top_1.v:41 Unused macro argument "f". |
| |
| [WARNI:PP0114] top_1.v:41 Undefined macro argument "g". |
| |
| [WARNI:PP0113] top_1.v:43 Unused macro argument "b". |
| |
| [WARNI:PP0114] top_1.v:43 Undefined macro argument "k". |
| |
| [WARNI:PP0114] top_1.v:43 Undefined macro argument "z". |
| |
| [INFO :PP0122] Preprocessing source file "top_2.v". |
| |
| [ERROR:PP0120] mode.vh:15 Illegal directive in design element "`timescale", |
| top_2.v:22 macro instance. |
| |
| [ERROR:PP0116] top_2.v:43 Illegal unterminated string: >>"start of string |
| <<. |
| |
| [ERROR:PP0116] top_2.v:45 Illegal unterminated string: >>"); |
| <<. |
| |
| [ERROR:PP0118] top_2.v:47 Unknown escaped sequence '\p'. |
| |
| [INFO :PP0123] Preprocessing include file "foo/inc.sv". |
| |
| [INFO :PP0122] Preprocessing source file "top_3.v". |
| |
| [ERROR:PP0102] top_3.v:16 Unknown macro "defaut_nettype". |
| |
| [WARNI:PP0103] top_3.v:18 Undefining an unknown macro "multipl". |
| |
| [ERROR:PP0120] mode.vh:15 Illegal directive in design element "`timescale", |
| top_3.v:25 macro instance. |
| |
| [ERROR:PP0107] top_3.v:35 Too many arguments (4) for macro "MACRO1", |
| mode.vh:42 macro definition takes 3. |
| |
| [ERROR:PP0109] top_3.v:37 Macro instantiation omits argument 3 (c) for "MACRO1", |
| mode.vh:42 No default value for argument 3 (c) in macro definition. |
| |
| [ERROR:PP0109] top_3.v:39 Macro instantiation omits argument 3 (c) for "MACRO1", |
| mode.vh:42 No default value for argument 3 (c) in macro definition. |
| |
| [ERROR:PP0110] top_3.v:41 Macro instantiation omits parenthesis for "MACRO1", |
| mode.vh:42 macro definition has arguments. |
| |
| [ERROR:PP0109] top_3.v:41 Macro instantiation omits argument 3 (c) for "MACRO1", |
| mode.vh:42 No default value for argument 3 (c) in macro definition. |
| |
| [ERROR:PP0107] top_3.v:45 Too many arguments (3) for macro "macro_with_args", |
| mode.vh:21 macro definition takes 2. |
| |
| [INFO :PP0122] Preprocessing source file "top_4.v". |
| |
| [WARNI:PP0103] top_4.v:15 Undefining an unknown macro "multipl". |
| |
| [ERROR:PP0120] mode.vh:15 Illegal directive in design element "`timescale", |
| top_4.v:34 macro instance. |
| |
| [INFO :PP0122] Preprocessing source file "/home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v". |
| |
| [INFO :PA0201] Parsing source file "builtin.sv". |
| |
| [INFO :PA0201] Parsing source file "top.v". |
| |
| [SYNTX:PA0207] mode.vh:27 Syntax error: mismatched input 'initial' expecting <EOF>, |
| initial $display("start", "msg1" , "msg2" , "end"); |
| ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top.v:34 col:0. |
| |
| [INFO :PA0201] Parsing source file "top_1.v". |
| |
| [SYNTX:PA0207] mode.vh:9 Syntax error: mismatched input 'initial' expecting <EOF>, |
| initial $display("start", "msg1" , "msg2" , "end"); |
| ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_1.v:34 col:0. |
| |
| [INFO :PA0201] Parsing source file "top_2.v". |
| |
| [SYNTX:PA0207] top_2.v:45 Syntax error: token recognition error at: '"start of string\n', |
| "start of string |
| ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_2.v:122 col:0. |
| |
| [INFO :PA0201] Parsing source file "top_3.v". |
| |
| [SYNTX:PA0207] top_3.v:6 Syntax error: mismatched input '1' expecting <EOF>, |
| 1 + 1 + 42 + 100 + c |
| ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_3.v:3 col:0. |
| |
| [INFO :PA0201] Parsing source file "top_4.v". |
| |
| [SYNTX:PA0207] top_4.v:51 Syntax error: token recognition error at: '\', |
| [a,b]+(300,400)+{500,600}+"400,600"+\escaped,here |
| ^-- ../../build/tests/UnitSimpleIncludeAndMacros/slpp_unit/work/top_4.v:127 col:36. |
| |
| [INFO :PA0201] Parsing source file "/home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:2 No timescale set for "FAKELIB_NAND2". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:5 No timescale set for "FAKELIB_NAND4". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:8 No timescale set for "FAKELIB_NOR2". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:11 No timescale set for "FAKELIB_INV". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:14 No timescale set for "FAKELIB_BUF". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:17 No timescale set for "FAKELIB_BUF_BIGLOAD". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:20 No timescale set for "FAKELIB_DFF". |
| |
| [WARNI:PA0205] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:25 No timescale set for "FAKELIB_DFF_PRIMITIVE". |
| |
| [INFO :PY0400] Processing source file "builtin.sv". |
| |
| [INFO :PY0400] Processing source file "top.v". |
| |
| [INFO :PY0400] Processing source file "top_1.v". |
| |
| [INFO :PY0400] Processing source file "top_2.v". |
| |
| [INFO :PY0400] Processing source file "top_3.v". |
| |
| [INFO :PY0400] Processing source file "top_4.v". |
| |
| [INFO :PY0400] Processing source file "/home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v". |
| |
| enterTop_level_rule |
| File: top.v , 2 |
| Text: `timescale 10 ns / 1 ... |
| enterNull_rule |
| File: top.v , 2 |
| Text: ... |
| enterSource_text |
| File: top.v , 2 |
| Text: `timescale 10 ns / 1 ... |
| enterDescription |
| File: top.v , 2 |
| Text: `timescale 10 ns / 1 ... |
| enterTop_directives |
| File: top.v , 2 |
| Text: `timescale 10 ns / 1 ... |
| enterTimescale_directive |
| File: top.v , 2 |
| Text: `timescale 10 ns / 1 ... |
| enterTop_level_rule |
| File: top_1.v , 34 |
| Text: initial $ display ( ... |
| enterNull_rule |
| File: top_1.v , 34 |
| Text: ... |
| enterSource_text |
| File: top_1.v , 34 |
| Text: ... |
| enterTop_level_rule |
| File: top_2.v , 34 |
| Text: initial $ display ( ... |
| enterNull_rule |
| File: top_2.v , 34 |
| Text: ... |
| enterSource_text |
| File: top_2.v , 34 |
| Text: ... |
| enterTop_level_rule |
| File: top_3.v , 3 |
| Text: 1 + 1 + 42 + 100 + c ... |
| enterNull_rule |
| File: top_3.v , 3 |
| Text: ... |
| enterSource_text |
| File: top_3.v , 3 |
| Text: ... |
| enterTop_level_rule |
| File: top_4.v , 34 |
| Text: initial $ display ( ... |
| enterNull_rule |
| File: top_4.v , 34 |
| Text: ... |
| enterSource_text |
| File: top_4.v , 34 |
| Text: ... |
| enterTop_level_rule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: `celldefine module F ... |
| enterNull_rule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: ... |
| enterSource_text |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: `celldefine module F ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: `celldefine ... |
| enterTop_directives |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: `celldefine ... |
| enterCelldefine_directive |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 1 |
| Text: `celldefine ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: module FAKELIB_NAND2 ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: module FAKELIB_NAND2 ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: module FAKELIB_NAND2 ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: FAKELIB_NAND2 ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: input IN0 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: IN0 ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: IN1 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 2 |
| Text: IN1 ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: assign OUT = ~ ( IN0 ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: assign OUT = ~ ( IN0 ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: assign OUT = ~ ( IN0 ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: assign OUT = ~ ( IN0 ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: OUT = ~ ( IN0 & IN1 ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: OUT = ~ ( IN0 & IN1 ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: ~ ( IN0 & IN1 ) ... |
| enterUnary_Tilda |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: ~ ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: ( IN0 & IN1 ) ... |
| enterMintypmax_expression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 & IN1 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 & IN1 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN0 ... |
| enterBinOp_BitwAnd |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: & ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN1 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN1 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN1 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 3 |
| Text: IN1 ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 4 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: module FAKELIB_NAND4 ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: module FAKELIB_NAND4 ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: module FAKELIB_NAND4 ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: FAKELIB_NAND4 ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: input IN0 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN0 ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN1 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN1 ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN2 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN2 ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN3 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 5 |
| Text: IN3 ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: assign OUT = ~ ( IN0 ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: assign OUT = ~ ( IN0 ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: assign OUT = ~ ( IN0 ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: assign OUT = ~ ( IN0 ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: OUT = ~ ( IN0 & IN1 ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: OUT = ~ ( IN0 & IN1 ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: ~ ( IN0 & IN1 & IN2 ... |
| enterUnary_Tilda |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: ~ ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: ( IN0 & IN1 & IN2 & ... |
| enterMintypmax_expression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 & IN1 & IN2 & IN ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 & IN1 & IN2 & IN ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 & IN1 & IN2 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 & IN1 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN0 ... |
| enterBinOp_BitwAnd |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: & ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN1 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN1 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN1 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN1 ... |
| enterBinOp_BitwAnd |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: & ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN2 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN2 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN2 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN2 ... |
| enterBinOp_BitwAnd |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: & ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN3 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN3 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN3 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 6 |
| Text: IN3 ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 7 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: module FAKELIB_NOR2 ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: module FAKELIB_NOR2 ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: module FAKELIB_NOR2 ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: FAKELIB_NOR2 ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: input IN0 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: IN0 ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: IN1 ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 8 |
| Text: IN1 ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: assign OUT = ~ ( IN1 ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: assign OUT = ~ ( IN1 ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: assign OUT = ~ ( IN1 ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: assign OUT = ~ ( IN1 ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: OUT = ~ ( IN1 | IN0 ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: OUT = ~ ( IN1 | IN0 ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: ~ ( IN1 | IN0 ) ... |
| enterUnary_Tilda |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: ~ ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: ( IN1 | IN0 ) ... |
| enterMintypmax_expression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 | IN0 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 | IN0 ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN1 ... |
| enterBinOp_BitwOr |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: | ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN0 ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN0 ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN0 ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 9 |
| Text: IN0 ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 10 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: module FAKELIB_INV ( ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: module FAKELIB_INV ( ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: module FAKELIB_INV ( ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: FAKELIB_INV ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: input IN ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 11 |
| Text: IN ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: assign OUT = ~ IN ; ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: assign OUT = ~ IN ; ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: assign OUT = ~ IN ; ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: assign OUT = ~ IN ; ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: OUT = ~ IN ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: OUT = ~ IN ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: ~ IN ... |
| enterUnary_Tilda |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: ~ ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: IN ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: IN ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 12 |
| Text: IN ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 13 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: module FAKELIB_BUF ( ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: module FAKELIB_BUF ( ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: module FAKELIB_BUF ( ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: FAKELIB_BUF ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: input IN ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 14 |
| Text: IN ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: assign OUT = IN ; ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: assign OUT = IN ; ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: assign OUT = IN ; ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: assign OUT = IN ; ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: OUT = IN ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: OUT = IN ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: IN ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: IN ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: IN ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 15 |
| Text: IN ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 16 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: module FAKELIB_BUF_B ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: module FAKELIB_BUF_B ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: module FAKELIB_BUF_B ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: FAKELIB_BUF_BIGLOAD ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: ( output OUT , input ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: output OUT ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: output ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: OUT ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: input IN ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 17 |
| Text: IN ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: assign OUT = IN ; ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: assign OUT = IN ; ... |
| enterModule_common_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: assign OUT = IN ; ... |
| enterContinuous_assign |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: assign OUT = IN ; ... |
| enterList_of_net_assignments |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: OUT = IN ... |
| enterNet_assignment |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: OUT = IN ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: OUT ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: OUT ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: OUT ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: IN ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: IN ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: IN ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 18 |
| Text: IN ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 19 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: module FAKELIB_DFF ( ... |
| enterModule_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: module FAKELIB_DFF ( ... |
| enterModule_ansi_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: module FAKELIB_DFF ( ... |
| enterModule_keyword |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: module ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: FAKELIB_DFF ... |
| enterList_of_port_declarations |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ( output reg Q , inp ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: output reg Q ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: output reg ... |
| enterPortDir_Out |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: output ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: reg ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: reg ... |
| enterData_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: reg ... |
| enterIntVec_TypeReg |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: reg ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: Q ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: input CLK ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: input ... |
| enterPortDir_Inp |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: input ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: CLK ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: RST_N ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: RST_N ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: SET_N ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: SET_N ... |
| enterAnsi_port_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: D ... |
| enterNet_port_header |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterNet_port_type |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterData_type_or_implicit |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 20 |
| Text: D ... |
| enterNon_port_module_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: FAKELIB_DFF_PRIMITIV ... |
| enterModule_or_generate_item |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: FAKELIB_DFF_PRIMITIV ... |
| enterUdp_instantiation |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: FAKELIB_DFF_PRIMITIV ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: FAKELIB_DFF_PRIMITIV ... |
| enterUdp_instance |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: dff ( Q , CLK , RST_ ... |
| enterName_of_instance |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: dff ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: dff ... |
| enterNet_lvalue |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: Q ... |
| enterPs_or_hierarchical_identifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: Q ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: Q ... |
| enterConstant_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: ... |
| enterConstant_bit_select |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: CLK ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: CLK ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: CLK ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: CLK ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: RST_N ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: RST_N ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: RST_N ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: RST_N ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: SET_N ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: SET_N ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: SET_N ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: SET_N ... |
| enterExpression |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: D ... |
| enterPrimary |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: D ... |
| enterPrimary_literal |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: D ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 21 |
| Text: D ... |
| enterEndmodule |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 22 |
| Text: endmodule ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 24 |
| Text: `endcelldefine ... |
| enterTop_directives |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 24 |
| Text: `endcelldefine ... |
| enterEndcelldefine_directive |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 24 |
| Text: `endcelldefine ... |
| enterDescription |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: primitive FAKELIB_DF ... |
| enterUdp_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: primitive FAKELIB_DF ... |
| enterUdp_ansi_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: primitive FAKELIB_DF ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: FAKELIB_DFF_PRIMITIV ... |
| enterUdp_declaration_port_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: output reg Q , input ... |
| enterUdp_output_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: output reg Q ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: Q ... |
| enterUdp_input_declaration |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: input CLK , RST_N , ... |
| enterIdentifier_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: CLK , RST_N , SET_N ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: CLK ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: RST_N ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: SET_N ... |
| enterIdentifier |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 25 |
| Text: D ... |
| enterUdp_body |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 26 |
| Text: table ? 0 ? ? : ? : ... |
| enterSequential_body |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 26 |
| Text: table ? 0 ? ? : ? : ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? 0 ? ? : ? : 0 ; ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? 0 ? ? ... |
| enterLevel_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? 0 ? ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: 0 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v ,[INFO :CP0300] Compilation... |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:14 Compile module "work@FAKELIB_BUF". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:17 Compile module "work@FAKELIB_BUF_BIGLOAD". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:20 Compile module "work@FAKELIB_DFF". |
| |
| [INFO :CP0305] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:25 Compile udp "work@FAKELIB_DFF_PRIMITIVE". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:11 Compile module "work@FAKELIB_INV". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:2 Compile module "work@FAKELIB_NAND2". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:5 Compile module "work@FAKELIB_NAND4". |
| |
| [INFO :CP0303] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:8 Compile module "work@FAKELIB_NOR2". |
| |
| [INFO :CP0302] builtin.sv:4 Compile class "work@mailbox". |
| |
| [INFO :CP0302] builtin.sv:33 Compile class "work@process". |
| |
| [INFO :CP0302] builtin.sv:58 Compile class "work@semaphore". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:14 Implicit port type (wire) for "OUT". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:17 Implicit port type (wire) for "OUT". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:11 Implicit port type (wire) for "OUT". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:2 Implicit port type (wire) for "OUT". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:5 Implicit port type (wire) for "OUT". |
| |
| [NOTE :CP0309] /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v:8 Implicit port type (wire) for "OUT". |
| |
| [INFO :EL0526] Design Elaboration... |
| |
| [NOTE :EL0508] Nb Top level modules: 0. |
| |
| [NOTE :EL0509] Max instance depth: 0. |
| |
| [NOTE :EL0510] Nb instances: 0. |
| |
| [NOTE :EL0511] Nb leaf instances: 0. |
| |
| [ FATAL] : 0 |
| [ SYNTAX] : 6 |
| [ ERROR] : 24 |
| [WARNING] : 18 |
| [ NOTE] : 12 |
| 28 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: 0 ... |
| enterOutput_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 28 |
| Text: 0 ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? 10 ? : ? : 1 ; ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? 10 ? ... |
| enterLevel_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? 10 ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: 10 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: 1 ... |
| enterOutput_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 29 |
| Text: 1 ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: p 110 : ? : 0 ; ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: p 110 ... |
| enterLevel_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: p 110 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: p ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: 110 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: 0 ... |
| enterOutput_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 30 |
| Text: 0 ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: p 111 : ? : 1 ; ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: p 111 ... |
| enterLevel_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: p 111 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: p ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: 111 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: 1 ... |
| enterOutput_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 31 |
| Text: 1 ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ( ? 0 ) 11 ? : ? : - ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ( ? 0 ) 11 ? ... |
| enterEdge_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ( ? 0 ) 11 ? ... |
| enterEdge_indicator |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ( ? 0 ) ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: 0 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: 11 ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 32 |
| Text: - ... |
| enterSequential_entry |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: ? 11 * : ? : - ; ... |
| enterSeq_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: ? 11 * ... |
| enterEdge_input_list |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: ? 11 * ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: ? ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: 11 ... |
| enterEdge_indicator |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: * ... |
| enterEdge_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: * ... |
| enterLevel_symbol |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: ? ... |
| enterNext_state |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 33 |
| Text: - ... |
| enterEndtable |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 34 |
| Text: endtable ... |
| enterEndprimitive |
| File: /home/alain/Surelog/tests/SimpleIncludeAndMacros/lib.v , 35 |
| Text: endprimitive ... |
| |
