fix bogus tests
Signed-off-by: Alain <alainmarcel@yahoo.com>
diff --git a/tests/SimpleConstraint/SimpleConstraint.log b/tests/SimpleConstraint/SimpleConstraint.log
index e141bc0..adf16c5 100644
--- a/tests/SimpleConstraint/SimpleConstraint.log
+++ b/tests/SimpleConstraint/SimpleConstraint.log
@@ -6,9 +6,9 @@
[INFO :PP0122] Preprocessing source file "top.sv".
-Preprocessing took 0.008s
+Preprocessing took 0.006s
-Preprocessing took 0.008s
+Preprocessing took 0.006s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
PP SSL Parsing: 0.000 top.sv
@@ -743,10 +743,10 @@
n<> u<721> t<Source_text> p<722> c<17> l<2>
n<> u<722> t<Top_level_rule> l<2>
Cache saving: 0.000000
-Parsing took 1.490s
-SLL Parsing: 0.036 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 0.962s
+SLL Parsing: 0.032 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-SLL Parsing: 1.446 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
+SLL Parsing: 0.924 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
Cache saving: 0.000000
[WARNI:PA0205] top.sv:4 No timescale set for "constaint_mode_ex".
@@ -765,7 +765,7 @@
[WARNI:CP0314] top.sv:4 Using programs is discouraged "work@constaint_mode_ex", programs are obsoleted by UVM.
-Compilation took 0.002s
+Compilation took 0.000s
[INFO :EL0526] Design Elaboration...
@@ -783,17 +783,17 @@
PROFILE
==============
Scan libraries took 0.000s
-Preprocessing took 0.008s
+Preprocessing took 0.006s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
PP SSL Parsing: 0.000 top.sv
-Parsing took 1.490s
-SLL Parsing: 0.036 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 0.962s
+SLL Parsing: 0.032 ../../build/tests/SimpleConstraint/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-SLL Parsing: 1.446 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
+SLL Parsing: 0.924 ../../build/tests/SimpleConstraint/slpp_all/work/top.sv
Cache saving: 0.000000
-Compilation took 0.002s
+Compilation took 0.000s
Elaboration took 0.000s
-Total time 1.500s
+Total time 0.968s
==============
[ FATAL] : 0
diff --git a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
index c2aa1f4..7841d6d 100644
--- a/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
+++ b/third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
@@ -842,9 +842,9 @@
[INFO :CP0302] uvm-1.2/src/reg/uvm_vreg_field.svh:379 Compile class "uvm_pkg::uvm_vreg_field_cbs".
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:131261 Compile class "work@amiq_svaunit_ex_simple_test_head_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:116951 Compile class "work@amiq_svaunit_ex_simple_test_head_sequence".
-[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:123945 Compile class "work@amiq_svaunit_ex_simple_test_sequence".
+[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:116790 Compile class "work@amiq_svaunit_ex_simple_test_sequence".
[INFO :CP0302] amiq_svaunit_ex_simple_pkg.sv:131753 Compile class "work@amiq_svaunit_ex_simple_test_suite".
diff --git a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
index 7379045..7ed8c72 100644
--- a/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
+++ b/third_party/tests/BuildOVMPkg/BuildOVMPkg.log
@@ -235,9 +235,9 @@
[INFO :PP0123] Preprocessing include file "../../UVM/ovm-2.1.2/src/compatibility/urm_meth_compatibility.svh".
-Preprocessing took 0.874s
+Preprocessing took 0.914s
-Preprocessing took 0.874s
+Preprocessing took 0.914s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
PP SSL Parsing: 0.002 ../../UVM/ovm-2.1.2/src/ovm_pkg.sv
@@ -247,10 +247,10 @@
[INFO :PA0201] Parsing source file "../../UVM/ovm-2.1.2/src/ovm_pkg.sv".
Cache saving: 0.000000
-Parsing took 46.342s
-SLL Parsing: 0.036 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 44.332s
+SLL Parsing: 0.032 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-LL Parsing: 45.376 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
+LL Parsing: 43.446 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
Cache saving: 0.000000
[WARNI:PA0205] ../../UVM/ovm-2.1.2/src/ovm_pkg.sv:23 No timescale set for "ovm_pkg".
@@ -817,7 +817,7 @@
[INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
-Compilation took 0.022s
+Compilation took 0.024s
[INFO :EL0526] Design Elaboration...
@@ -829,23 +829,23 @@
[NOTE :EL0511] Nb leaf instances: 0.
-Elaboration took 0.020s
+Elaboration took 0.018s
==============
PROFILE
==============
Scan libraries took 0.000s
-Preprocessing took 0.874s
+Preprocessing took 0.914s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
PP SSL Parsing: 0.002 ../../UVM/ovm-2.1.2/src/ovm_pkg.sv
-Parsing took 46.342s
-SLL Parsing: 0.036 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 44.332s
+SLL Parsing: 0.032 ../../../build/tests/BuildOVMPkg/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-LL Parsing: 45.376 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
+LL Parsing: 43.446 ../../../build/tests/BuildOVMPkg/slpp_all/work/__/__/UVM/ovm-2.1.2/src/ovm_pkg.sv
Cache saving: 0.000000
-Compilation took 0.022s
-Elaboration took 0.020s
-Total time 47.260s
+Compilation took 0.024s
+Elaboration took 0.018s
+Total time 45.290s
==============
[ FATAL] : 0
diff --git a/third_party/tests/Scr1/Scr1.log b/third_party/tests/Scr1/Scr1.log
index edb0128..eba0a2d 100644
--- a/third_party/tests/Scr1/Scr1.log
+++ b/third_party/tests/Scr1/Scr1.log
@@ -6,17 +6,17 @@
[WARNI:PP0103] src/includes/scr1_arch_description.svh:63 Undefining an unknown macro "SCR1_CLKCTRL_EN".
-Preprocessing took 0.486s
+Preprocessing took 0.434s
-Preprocessing took 0.486s
+Preprocessing took 0.434s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
-PP SSL Parsing: 0.008 src/pipeline/scr1_pipe_hdu.sv
+PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_hdu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_tdu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_ipic.sv
-PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_csr.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_csr.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_exu.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ialu.sv
-PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_idu.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_idu.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ifu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_lsu.sv
PP SSL Parsing: 0.000 src/pipeline/scr1_pipe_mprf.sv
@@ -26,9 +26,9 @@
PP SSL Parsing: 0.000 src/core/scr1_clk_ctrl.sv
PP SSL Parsing: 0.000 src/core/scr1_tapc_shift_reg.sv
PP SSL Parsing: 0.002 src/core/scr1_tapc.sv
-PP SSL Parsing: 0.002 src/core/scr1_tapc_synchronizer.sv
+PP SSL Parsing: 0.000 src/core/scr1_tapc_synchronizer.sv
PP SSL Parsing: 0.002 src/core/scr1_core_top.sv
-PP SSL Parsing: 0.008 src/core/scr1_dm.sv
+PP SSL Parsing: 0.006 src/core/scr1_dm.sv
PP SSL Parsing: 0.000 src/core/scr1_dmi.sv
PP SSL Parsing: 0.002 src/core/scr1_scu.sv
PP SSL Parsing: 0.002 src/top/scr1_dmem_router.sv
@@ -38,7 +38,7 @@
PP SSL Parsing: 0.002 src/top/scr1_timer.sv
PP SSL Parsing: 0.002 src/top/scr1_mem_axi.sv
PP SSL Parsing: 0.004 src/top/scr1_top_axi.sv
-PP SSL Parsing: 0.004 src/pipeline/scr1_tracelog.sv
+PP SSL Parsing: 0.002 src/pipeline/scr1_tracelog.sv
PP SSL Parsing: 0.002 src/tb/scr1_memory_tb_axi.sv
PP SSL Parsing: 0.004 src/tb/scr1_top_tb_axi.sv
@@ -74,24 +74,24 @@
Cache saving: 0.000000
Cache saving: 0.000000
Cache saving: 0.000000
-Parsing took 20.594s
-SLL Parsing: 0.060 ../../../build/tests/Scr1/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 17.516s
+SLL Parsing: 0.032 ../../../build/tests/Scr1/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-SLL Parsing: 5.062 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_hdu.sv
+SLL Parsing: 2.952 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_hdu.sv
Cache saving: 0.002000
-SLL Parsing: 1.364 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_tdu.sv
+SLL Parsing: 1.004 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_tdu.sv
Cache saving: 0.002000
-LL Parsing: 1.522 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_ipic.sv
+LL Parsing: 1.154 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_ipic.sv
Cache saving: 0.000000
-SLL Parsing: 0.374 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_csr.sv
+SLL Parsing: 0.354 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_csr.sv
Cache saving: 0.004000
-SLL Parsing: 0.528 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_exu.sv
+SLL Parsing: 0.534 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_exu.sv
Cache saving: 0.002000
-LL Parsing: 1.556 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ialu.sv
+LL Parsing: 1.484 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ialu.sv
Cache saving: 0.000000
-SLL Parsing: 0.746 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_idu.sv
+SLL Parsing: 0.664 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_idu.sv
Cache saving: 0.002000
-SLL Parsing: 0.484 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ifu.sv
+SLL Parsing: 0.434 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ifu.sv
Cache saving: 0.002000
SLL Parsing: 0.064 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_lsu.sv
Cache saving: 0.002000
@@ -107,37 +107,37 @@
Cache saving: 0.000000
SLL Parsing: 0.104 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_shift_reg.sv
Cache saving: 0.000000
-SLL Parsing: 0.246 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc.sv
+SLL Parsing: 0.244 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc.sv
Cache saving: 0.002000
SLL Parsing: 0.178 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_synchronizer.sv
Cache saving: 0.002000
-SLL Parsing: 0.212 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
+SLL Parsing: 0.210 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
Cache saving: 0.004000
SLL Parsing: 0.616 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dm.sv
Cache saving: 0.004000
SLL Parsing: 0.152 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dmi.sv
Cache saving: 0.002000
-SLL Parsing: 0.254 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
+SLL Parsing: 0.290 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
Cache saving: 0.000000
-SLL Parsing: 0.026 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
+SLL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
Cache saving: 0.000000
-SLL Parsing: 0.006 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
+SLL Parsing: 0.008 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
Cache saving: 0.000000
-SLL Parsing: 0.038 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
+SLL Parsing: 0.044 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
Cache saving: 0.000000
-SLL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
+SLL Parsing: 0.034 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
Cache saving: 0.000000
-SLL Parsing: 0.114 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
+SLL Parsing: 0.130 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
Cache saving: 0.000000
-LL Parsing: 0.910 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
+LL Parsing: 1.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
Cache saving: 0.000000
-SLL Parsing: 0.078 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
+SLL Parsing: 0.086 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
Cache saving: 0.000000
-SLL Parsing: 0.416 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
+SLL Parsing: 0.450 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
Cache saving: 0.000000
-LL Parsing: 2.948 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
+LL Parsing: 2.834 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
Cache saving: 0.000000
-SLL Parsing: 1.348 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
+SLL Parsing: 1.290 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
Cache saving: 0.000000
[WARNI:PA0205] src/pipeline/scr1_pipe_hdu.sv:13 No timescale set for "scr1_pipe_hdu".
@@ -212,15 +212,15 @@
PROFILE
==============
Scan libraries took 0.000s
-Preprocessing took 0.486s
+Preprocessing took 0.434s
PP SSL Parsing: 0.000 /home/alain/Surelog/build/dist/Release//sv/builtin.sv
-PP SSL Parsing: 0.008 src/pipeline/scr1_pipe_hdu.sv
+PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_hdu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_tdu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_ipic.sv
-PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_csr.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_csr.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_exu.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ialu.sv
-PP SSL Parsing: 0.006 src/pipeline/scr1_pipe_idu.sv
+PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_idu.sv
PP SSL Parsing: 0.004 src/pipeline/scr1_pipe_ifu.sv
PP SSL Parsing: 0.002 src/pipeline/scr1_pipe_lsu.sv
PP SSL Parsing: 0.000 src/pipeline/scr1_pipe_mprf.sv
@@ -230,9 +230,9 @@
PP SSL Parsing: 0.000 src/core/scr1_clk_ctrl.sv
PP SSL Parsing: 0.000 src/core/scr1_tapc_shift_reg.sv
PP SSL Parsing: 0.002 src/core/scr1_tapc.sv
-PP SSL Parsing: 0.002 src/core/scr1_tapc_synchronizer.sv
+PP SSL Parsing: 0.000 src/core/scr1_tapc_synchronizer.sv
PP SSL Parsing: 0.002 src/core/scr1_core_top.sv
-PP SSL Parsing: 0.008 src/core/scr1_dm.sv
+PP SSL Parsing: 0.006 src/core/scr1_dm.sv
PP SSL Parsing: 0.000 src/core/scr1_dmi.sv
PP SSL Parsing: 0.002 src/core/scr1_scu.sv
PP SSL Parsing: 0.002 src/top/scr1_dmem_router.sv
@@ -242,27 +242,27 @@
PP SSL Parsing: 0.002 src/top/scr1_timer.sv
PP SSL Parsing: 0.002 src/top/scr1_mem_axi.sv
PP SSL Parsing: 0.004 src/top/scr1_top_axi.sv
-PP SSL Parsing: 0.004 src/pipeline/scr1_tracelog.sv
+PP SSL Parsing: 0.002 src/pipeline/scr1_tracelog.sv
PP SSL Parsing: 0.002 src/tb/scr1_memory_tb_axi.sv
PP SSL Parsing: 0.004 src/tb/scr1_top_tb_axi.sv
-Parsing took 20.594s
-SLL Parsing: 0.060 ../../../build/tests/Scr1/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
+Parsing took 17.516s
+SLL Parsing: 0.032 ../../../build/tests/Scr1/slpp_all/work//home/alain/Surelog/build/dist/Release//sv/builtin.sv
Cache saving: 0.000000
-SLL Parsing: 5.062 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_hdu.sv
+SLL Parsing: 2.952 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_hdu.sv
Cache saving: 0.002000
-SLL Parsing: 1.364 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_tdu.sv
+SLL Parsing: 1.004 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_tdu.sv
Cache saving: 0.002000
-LL Parsing: 1.522 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_ipic.sv
+LL Parsing: 1.154 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_ipic.sv
Cache saving: 0.000000
-SLL Parsing: 0.374 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_csr.sv
+SLL Parsing: 0.354 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_csr.sv
Cache saving: 0.004000
-SLL Parsing: 0.528 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_exu.sv
+SLL Parsing: 0.534 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_exu.sv
Cache saving: 0.002000
-LL Parsing: 1.556 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ialu.sv
+LL Parsing: 1.484 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ialu.sv
Cache saving: 0.000000
-SLL Parsing: 0.746 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_idu.sv
+SLL Parsing: 0.664 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_idu.sv
Cache saving: 0.002000
-SLL Parsing: 0.484 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ifu.sv
+SLL Parsing: 0.434 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_ifu.sv
Cache saving: 0.002000
SLL Parsing: 0.064 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_pipe_lsu.sv
Cache saving: 0.002000
@@ -278,39 +278,39 @@
Cache saving: 0.000000
SLL Parsing: 0.104 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_shift_reg.sv
Cache saving: 0.000000
-SLL Parsing: 0.246 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc.sv
+SLL Parsing: 0.244 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc.sv
Cache saving: 0.002000
SLL Parsing: 0.178 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_tapc_synchronizer.sv
Cache saving: 0.002000
-SLL Parsing: 0.212 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
+SLL Parsing: 0.210 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_core_top.sv
Cache saving: 0.004000
SLL Parsing: 0.616 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dm.sv
Cache saving: 0.004000
SLL Parsing: 0.152 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_dmi.sv
Cache saving: 0.002000
-SLL Parsing: 0.254 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
+SLL Parsing: 0.290 ../../../build/tests/Scr1/slpp_all/work/src/core/scr1_scu.sv
Cache saving: 0.000000
-SLL Parsing: 0.026 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
+SLL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dmem_router.sv
Cache saving: 0.000000
-SLL Parsing: 0.006 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
+SLL Parsing: 0.008 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_imem_router.sv
Cache saving: 0.000000
-SLL Parsing: 0.038 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
+SLL Parsing: 0.044 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_dp_memory.sv
Cache saving: 0.000000
-SLL Parsing: 0.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
+SLL Parsing: 0.034 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_tcm.sv
Cache saving: 0.000000
-SLL Parsing: 0.114 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
+SLL Parsing: 0.130 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_timer.sv
Cache saving: 0.000000
-LL Parsing: 0.910 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
+LL Parsing: 1.030 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_mem_axi.sv
Cache saving: 0.000000
-SLL Parsing: 0.078 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
+SLL Parsing: 0.086 ../../../build/tests/Scr1/slpp_all/work/src/top/scr1_top_axi.sv
Cache saving: 0.000000
-SLL Parsing: 0.416 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
+SLL Parsing: 0.450 ../../../build/tests/Scr1/slpp_all/work/src/pipeline/scr1_tracelog.sv
Cache saving: 0.000000
-LL Parsing: 2.948 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
+LL Parsing: 2.834 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_memory_tb_axi.sv
Cache saving: 0.000000
-SLL Parsing: 1.348 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
+SLL Parsing: 1.290 ../../../build/tests/Scr1/slpp_all/work/src/tb/scr1_top_tb_axi.sv
Cache saving: 0.000000
-Total time 21.082s
+Total time 17.952s
==============
[ FATAL] : 0
diff --git a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
index 4e88d15..20220f7 100644
--- a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
+++ b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.log
@@ -14,151 +14,96 @@
[WARNI:PP0103] ./rtl/openMSP430_undefines.v:254 Undefining an unknown macro "PER_CUSTOM_SIZE".
-[SYNTX:PA0207] sim/sieve.v:1 Syntax error: missing {'new', 'byte', 'bit', 'logic', 'signed', 'unsigned', 'var', 'context', 'expect', 'soft', 'global', 'do', 'this', 'randomize', 'final', 'sample', Escaped_identifier, Simple_identifier} at '[',
-pmem[ 512] = 16'h4031;
- ^-- ../../../build/tests/YosysBigSimOpenMsp/slpp_unit/work/sim/sieve.v:1 col:4.
-
-[WARNI:PA0205] rtl/omsp_clock_mux.v:44 No timescale set for "omsp_clock_mux".
-
[WARNI:PA0205] rtl/omsp_sync_cell.v:44 No timescale set for "omsp_sync_cell".
-[WARNI:PA0205] rtl/omsp_and_gate.v:44 No timescale set for "omsp_and_gate".
-
-[WARNI:PA0205] rtl/omsp_clock_gate.v:44 No timescale set for "omsp_clock_gate".
-
[WARNI:PA0205] rtl/omsp_sync_reset.v:44 No timescale set for "omsp_sync_reset".
-[WARNI:PA0205] rtl/omsp_scan_mux.v:44 No timescale set for "omsp_scan_mux".
-
[INFO :CP0300] Compilation...
-[INFO :CP0303] rtl/omsp_alu.v:47 Compile module "work@omsp_alu".
+[INFO :CP0303] rtl/omsp_alu.v:1280 Compile module "work@omsp_alu".
-[INFO :CP0303] rtl/omsp_and_gate.v:44 Compile module "work@omsp_and_gate".
+[INFO :CP0303] rtl/omsp_clock_module.v:1280 Compile module "work@omsp_clock_module".
-[INFO :CP0303] rtl/omsp_clock_gate.v:44 Compile module "work@omsp_clock_gate".
+[INFO :CP0303] rtl/omsp_dbg.v:1280 Compile module "work@omsp_dbg".
-[INFO :CP0303] rtl/omsp_clock_module.v:47 Compile module "work@omsp_clock_module".
+[INFO :CP0303] rtl/omsp_dbg_uart.v:1280 Compile module "work@omsp_dbg_uart".
-[INFO :CP0303] rtl/omsp_clock_mux.v:44 Compile module "work@omsp_clock_mux".
+[INFO :CP0303] rtl/omsp_execution_unit.v:1280 Compile module "work@omsp_execution_unit".
-[INFO :CP0303] rtl/omsp_dbg.v:47 Compile module "work@omsp_dbg".
+[INFO :CP0303] rtl/omsp_frontend.v:1280 Compile module "work@omsp_frontend".
-[INFO :CP0303] rtl/omsp_dbg_hwbrk.v:47 Compile module "work@omsp_dbg_hwbrk".
+[INFO :CP0303] rtl/omsp_mem_backbone.v:1280 Compile module "work@omsp_mem_backbone".
-[INFO :CP0303] rtl/omsp_dbg_i2c.v:47 Compile module "work@omsp_dbg_i2c".
+[INFO :CP0303] rtl/omsp_multiplier.v:1280 Compile module "work@omsp_multiplier".
-[INFO :CP0303] rtl/omsp_dbg_uart.v:47 Compile module "work@omsp_dbg_uart".
+[INFO :CP0303] rtl/omsp_register_file.v:1280 Compile module "work@omsp_register_file".
-[INFO :CP0303] rtl/omsp_execution_unit.v:47 Compile module "work@omsp_execution_unit".
-
-[INFO :CP0303] rtl/omsp_frontend.v:47 Compile module "work@omsp_frontend".
-
-[INFO :CP0303] rtl/omsp_mem_backbone.v:47 Compile module "work@omsp_mem_backbone".
-
-[INFO :CP0303] rtl/omsp_multiplier.v:47 Compile module "work@omsp_multiplier".
-
-[INFO :CP0303] rtl/omsp_register_file.v:47 Compile module "work@omsp_register_file".
-
-[INFO :CP0303] rtl/omsp_scan_mux.v:44 Compile module "work@omsp_scan_mux".
-
-[INFO :CP0303] rtl/omsp_sfr.v:48 Compile module "work@omsp_sfr".
+[INFO :CP0303] rtl/omsp_sfr.v:1281 Compile module "work@omsp_sfr".
[INFO :CP0303] rtl/omsp_sync_cell.v:44 Compile module "work@omsp_sync_cell".
[INFO :CP0303] rtl/omsp_sync_reset.v:44 Compile module "work@omsp_sync_reset".
-[INFO :CP0303] rtl/omsp_wakeup_cell.v:47 Compile module "work@omsp_wakeup_cell".
+[INFO :CP0303] rtl/omsp_watchdog.v:1280 Compile module "work@omsp_watchdog".
-[INFO :CP0303] rtl/omsp_watchdog.v:47 Compile module "work@omsp_watchdog".
+[INFO :CP0303] rtl/openMSP430.v:1280 Compile module "work@openMSP430".
-[INFO :CP0303] rtl/openMSP430.v:47 Compile module "work@openMSP430".
+[INFO :CP0303] sim/bench.v:851 Compile module "work@testbench".
-[INFO :CP0303] sim/bench.v:6 Compile module "work@testbench".
-
-[NOTE :CP0309] rtl/omsp_alu.v:50 Implicit port type (wire) for "alu_out",
+[NOTE :CP0309] rtl/omsp_alu.v:1283 Implicit port type (wire) for "alu_out",
there are 3 more instances of this message.
-[NOTE :CP0309] rtl/omsp_and_gate.v:47 Implicit port type (wire) for "y".
-
-[NOTE :CP0309] rtl/omsp_clock_gate.v:47 Implicit port type (wire) for "gclk".
-
-[NOTE :CP0309] rtl/omsp_clock_module.v:50 Implicit port type (wire) for "aclk",
+[NOTE :CP0309] rtl/omsp_clock_module.v:1283 Implicit port type (wire) for "aclk",
there are 14 more instances of this message.
-[NOTE :CP0309] rtl/omsp_clock_mux.v:47 Implicit port type (wire) for "clk_out".
-
-[NOTE :CP0309] rtl/omsp_dbg.v:50 Implicit port type (wire) for "dbg_cpu_reset",
+[NOTE :CP0309] rtl/omsp_dbg.v:1283 Implicit port type (wire) for "dbg_cpu_reset",
there are 9 more instances of this message.
-[NOTE :CP0309] rtl/omsp_dbg_hwbrk.v:50 Implicit port type (wire) for "brk_halt",
+[NOTE :CP0309] rtl/omsp_dbg_uart.v:1284 Implicit port type (wire) for "dbg_din",
there are 2 more instances of this message.
-[NOTE :CP0309] rtl/omsp_dbg_i2c.v:51 Implicit port type (wire) for "dbg_din".
-
-[NOTE :CP0309] rtl/omsp_dbg_uart.v:51 Implicit port type (wire) for "dbg_din",
-there are 2 more instances of this message.
-
-[NOTE :CP0309] rtl/omsp_execution_unit.v:50 Implicit port type (wire) for "cpuoff",
+[NOTE :CP0309] rtl/omsp_execution_unit.v:1283 Implicit port type (wire) for "cpuoff",
there are 11 more instances of this message.
-[NOTE :CP0309] rtl/omsp_frontend.v:51 Implicit port type (wire) for "decode_noirq",
+[NOTE :CP0309] rtl/omsp_frontend.v:1284 Implicit port type (wire) for "decode_noirq",
there are 11 more instances of this message.
-[NOTE :CP0309] rtl/omsp_mem_backbone.v:50 Implicit port type (wire) for "dbg_mem_din",
+[NOTE :CP0309] rtl/omsp_mem_backbone.v:1283 Implicit port type (wire) for "dbg_mem_din",
there are 15 more instances of this message.
-[NOTE :CP0309] rtl/omsp_multiplier.v:50 Implicit port type (wire) for "per_dout".
+[NOTE :CP0309] rtl/omsp_multiplier.v:1283 Implicit port type (wire) for "per_dout".
-[NOTE :CP0309] rtl/omsp_register_file.v:50 Implicit port type (wire) for "cpuoff",
+[NOTE :CP0309] rtl/omsp_register_file.v:1283 Implicit port type (wire) for "cpuoff",
there are 9 more instances of this message.
-[NOTE :CP0309] rtl/omsp_scan_mux.v:47 Implicit port type (wire) for "data_out".
-
-[NOTE :CP0309] rtl/omsp_sfr.v:51 Implicit port type (wire) for "cpu_id",
+[NOTE :CP0309] rtl/omsp_sfr.v:1284 Implicit port type (wire) for "cpu_id",
there are 5 more instances of this message.
[NOTE :CP0309] rtl/omsp_sync_cell.v:47 Implicit port type (wire) for "data_out".
[NOTE :CP0309] rtl/omsp_sync_reset.v:47 Implicit port type (wire) for "rst_s".
-[NOTE :CP0309] rtl/omsp_watchdog.v:50 Implicit port type (wire) for "per_dout",
+[NOTE :CP0309] rtl/omsp_watchdog.v:1283 Implicit port type (wire) for "per_dout",
there are 3 more instances of this message.
-[NOTE :CP0309] rtl/openMSP430.v:50 Implicit port type (wire) for "aclk",
+[NOTE :CP0309] rtl/openMSP430.v:1283 Implicit port type (wire) for "aclk",
there are 25 more instances of this message.
[INFO :EL0526] Design Elaboration...
-[NOTE :EL0503] sim/bench.v:6 Top level module "work@testbench".
+[NOTE :EL0503] sim/bench.v:851 Top level module "work@testbench".
-[NOTE :EL0503] rtl/omsp_clock_mux.v:44 Top level module "work@omsp_clock_mux".
-
-[NOTE :EL0503] rtl/omsp_wakeup_cell.v:47 Top level module "work@omsp_wakeup_cell".
-
-[NOTE :EL0503] rtl/omsp_and_gate.v:44 Top level module "work@omsp_and_gate".
-
-[NOTE :EL0503] rtl/omsp_clock_gate.v:44 Top level module "work@omsp_clock_gate".
-
-[NOTE :EL0503] rtl/omsp_scan_mux.v:44 Top level module "work@omsp_scan_mux".
-
-[NOTE :EL0503] rtl/omsp_dbg_i2c.v:47 Top level module "work@omsp_dbg_i2c".
-
-[NOTE :EL0503] rtl/omsp_dbg_hwbrk.v:47 Top level module "work@omsp_dbg_hwbrk".
-
-[NOTE :EL0504] Multiple top level modules in design.
-
-[NOTE :EL0508] Nb Top level modules: 8.
+[NOTE :EL0508] Nb Top level modules: 1.
[NOTE :EL0509] Max instance depth: 5.
-[NOTE :EL0510] Nb instances: 27.
+[NOTE :EL0510] Nb instances: 18.
-[NOTE :EL0511] Nb leaf instances: 17.
+[NOTE :EL0511] Nb leaf instances: 9.
[ FATAL] : 0
-[ SYNTAX] : 1
+[ SYNTAX] : 0
[ ERROR] : 0
-[WARNING] : 12
-[ NOTE] : 33
+[WARNING] : 8
+[ NOTE] : 19
diff --git a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.sl b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.sl
index f632dbc..08c4f6a 100644
--- a/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.sl
+++ b/third_party/tests/YosysBigSim/openmsp430/YosysBigSimOpenMsp.sl
@@ -1 +1 @@
- -writepp -parse -mt max -nopython -fileunit */*.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
+ -writepp -parse -mt max -nopython -fileunit rtl/openMSP430.v rtl/omsp_clock_module.v rtl/omsp_dbg.v rtl/omsp_execution_unit.v rtl/omsp_frontend.v rtl/omsp_mem_backbone.v rtl/omsp_multiplier.v rtl/omsp_sfr.v rtl/omsp_watchdog.v rtl/omsp_alu.v rtl/omsp_dbg_uart.v rtl/omsp_register_file.v rtl/omsp_sync_cell.v rtl/omsp_sync_reset.v sim/bench.v +incdir+./rtl/+./sim/ -nobuiltin -nocache
diff --git a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log
index 23eeabc..6bc0f9d 100644
--- a/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log
+++ b/third_party/tests/YosysBigSim/reed_solomon_decoder/YosysBigSimReed.log
@@ -2,11 +2,96 @@
[INFO :CM0020] Separate compilation-unit mode is on.
-[ERROR:PP0125] Cannot read the file's content "rtl/BM_lamda.v". Only UTF-8 is supported.
+[WARNI:PA0205] sim/RS_dec_tb.v:3 No timescale set for "testbench".
+
+[WARNI:PA0205] rtl/RS_dec.v:21 No timescale set for "RS_dec".
+
+[WARNI:PA0205] rtl/out_stage.v:21 No timescale set for "out_stage".
+
+[WARNI:PA0205] rtl/GF_matrix_dec.v:21 No timescale set for "GF_matrix_dec".
+
+[WARNI:PA0205] rtl/GF_mult_add_syndromes.v:28 No timescale set for "GF_mult_add_syndromes".
+
+[WARNI:PA0205] rtl/lamda_roots.v:21 No timescale set for "lamda_roots".
+
+[WARNI:PA0205] rtl/Omega_Phy.v:21 No timescale set for "Omega_Phy".
+
+[WARNI:PA0205] rtl/transport_in2out.v:22 No timescale set for "transport_in2out".
+
+[WARNI:PA0205] rtl/GF_matrix_ascending_binary.v:20 No timescale set for "GF_matrix_ascending_binary".
+
+[WARNI:PA0205] rtl/DP_RAM.v:18 No timescale set for "DP_RAM".
+
+[WARNI:PA0205] rtl/error_correction.v:20 No timescale set for "error_correction".
+
+[WARNI:PA0205] rtl/BM_lamda.v:20 No timescale set for "BM_lamda".
+
+[WARNI:PA0205] rtl/input_syndromes.v:24 No timescale set for "input_syndromes".
+
+[INFO :CP0300] Compilation...
+
+[INFO :CP0303] rtl/BM_lamda.v:20 Compile module "work@BM_lamda".
+
+[INFO :CP0303] rtl/DP_RAM.v:18 Compile module "work@DP_RAM".
+
+[INFO :CP0303] rtl/GF_matrix_ascending_binary.v:20 Compile module "work@GF_matrix_ascending_binary".
+
+[INFO :CP0303] rtl/GF_matrix_dec.v:21 Compile module "work@GF_matrix_dec".
+
+[INFO :CP0303] rtl/GF_mult_add_syndromes.v:28 Compile module "work@GF_mult_add_syndromes".
+
+[INFO :CP0303] rtl/Omega_Phy.v:21 Compile module "work@Omega_Phy".
+
+[INFO :CP0303] rtl/RS_dec.v:21 Compile module "work@RS_dec".
+
+[INFO :CP0303] rtl/error_correction.v:20 Compile module "work@error_correction".
+
+[INFO :CP0303] rtl/input_syndromes.v:24 Compile module "work@input_syndromes".
+
+[INFO :CP0303] rtl/lamda_roots.v:21 Compile module "work@lamda_roots".
+
+[INFO :CP0303] rtl/out_stage.v:21 Compile module "work@out_stage".
+
+[INFO :CP0303] sim/RS_dec_tb.v:3 Compile module "work@testbench".
+
+[INFO :CP0303] rtl/transport_in2out.v:22 Compile module "work@transport_in2out".
+
+[NOTE :CP0309] rtl/BM_lamda.v:40 Implicit port type (wire) for "add_pow2",
+there are 9 more instances of this message.
+
+[NOTE :CP0309] rtl/Omega_Phy.v:44 Implicit port type (wire) for "add_pow2",
+there are 20 more instances of this message.
+
+[NOTE :CP0309] rtl/RS_dec.v:29 Implicit port type (wire) for "Out_byte",
+there are 2 more instances of this message.
+
+[NOTE :CP0309] rtl/error_correction.v:44 Implicit port type (wire) for "add_pow2",
+there are 8 more instances of this message.
+
+[NOTE :CP0309] rtl/input_syndromes.v:38 Implicit port type (wire) for "s1",
+there are 15 more instances of this message.
+
+[NOTE :CP0309] rtl/lamda_roots.v:30 Implicit port type (wire) for "add_GF_dec1",
+there are 8 more instances of this message.
+
+[NOTE :CP0309] rtl/transport_in2out.v:32 Implicit port type (wire) for "WE",
+there are 1 more instances of this message.
+
+[INFO :EL0526] Design Elaboration...
+
+[NOTE :EL0503] sim/RS_dec_tb.v:3 Top level module "work@testbench".
+
+[NOTE :EL0508] Nb Top level modules: 1.
+
+[NOTE :EL0509] Max instance depth: 5.
+
+[NOTE :EL0510] Nb instances: 26.
+
+[NOTE :EL0511] Nb leaf instances: 0.
[ FATAL] : 0
[ SYNTAX] : 0
-[ ERROR] : 1
-[WARNING] : 0
-[ NOTE] : 0
+[ ERROR] : 0
+[WARNING] : 13
+[ NOTE] : 12
diff --git a/third_party/tests/YosysBigSim/reed_solomon_decoder/rtl/BM_lamda.v b/third_party/tests/YosysBigSim/reed_solomon_decoder/rtl/BM_lamda.v
index 63e2859..3f74515 100644
--- a/third_party/tests/YosysBigSim/reed_solomon_decoder/rtl/BM_lamda.v
+++ b/third_party/tests/YosysBigSim/reed_solomon_decoder/rtl/BM_lamda.v
@@ -18,7 +18,7 @@
module BM_lamda
-//// use Berlekamp Masseys Algorithm to calculate lamda polynomial
+//// use Berlekamp Massey Algorithm to calculate lamda polynomial
(
input clk, // input clock planned to be 56 Mhz
input reset, // active high asynchronous reset
@@ -324,4 +324,4 @@
end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log
index 01fce94..35bbcfd 100644
--- a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log
+++ b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.log
@@ -1,38 +1,30 @@
-[INFO :CM0023] Creating log file ../../../build/tests/YosysOldUsb/slpp_unit/surelog.log.
+[INFO :CM0023] Creating log file ../../../build/tests/YosysOldUsb/slpp_all/surelog.log.
-[INFO :CM0020] Separate compilation-unit mode is on.
-
-[WARNI:PA0205] cache/synth.v:1 No timescale set for "usb_phy".
-
-[WARNI:PA0205] cache/synth.v:109 No timescale set for "usb_rx_phy".
-
-[WARNI:PA0205] cache/synth.v:645 No timescale set for "usb_tx_phy".
+[WARNI:PA0205] rtl/usb_phy.v:76 No timescale set for "usb_phy".
[INFO :CP0300] Compilation...
-[INFO :CP0303] cache/synth.v:1 Compile module "work@usb_phy".
+[INFO :CP0303] rtl/usb_phy.v:76 Compile module "work@usb_phy".
-[INFO :CP0303] cache/synth.v:109 Compile module "work@usb_rx_phy".
+[INFO :CP0303] rtl/usb_rx_phy.v:78 Compile module "work@usb_rx_phy".
-[INFO :CP0303] cache/synth.v:645 Compile module "work@usb_tx_phy".
+[INFO :CP0303] rtl/usb_tx_phy.v:76 Compile module "work@usb_tx_phy".
-[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "txdp",
+[INFO :CP0302] builtin.sv:4 Compile class "work@mailbox".
+
+[INFO :CP0302] builtin.sv:33 Compile class "work@process".
+
+[INFO :CP0302] builtin.sv:58 Compile class "work@semaphore".
+
+[NOTE :CP0309] rtl/usb_phy.v:79 Implicit port type (wire) for "txdp",
there are 8 more instances of this message.
-[NOTE :CP0309] cache/synth.v:109 Implicit port type (wire) for "RxError_o".
+[NOTE :CP0309] rtl/usb_rx_phy.v:84 Implicit port type (wire) for "RxValid_o",
+there are 4 more instances of this message.
[INFO :EL0526] Design Elaboration...
-[NOTE :EL0503] cache/synth.v:1 Top level module "work@usb_phy".
-
-[WARNI:EL0505] rtl/usb_phy.v:76 Multiply defined module "work@usb_phy",
- cache/synth.v:1 previous definition.
-
-[WARNI:EL0505] rtl/usb_rx_phy.v:78 Multiply defined module "work@usb_rx_phy",
- cache/synth.v:109 previous definition.
-
-[WARNI:EL0505] rtl/usb_tx_phy.v:76 Multiply defined module "work@usb_tx_phy",
- cache/synth.v:645 previous definition.
+[NOTE :EL0503] rtl/usb_phy.v:76 Top level module "work@usb_phy".
[NOTE :EL0508] Nb Top level modules: 1.
@@ -40,11 +32,11 @@
[NOTE :EL0510] Nb instances: 3.
-[NOTE :EL0511] Nb leaf instances: 2.
+[NOTE :EL0511] Nb leaf instances: 0.
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
-[WARNING] : 6
+[WARNING] : 1
[ NOTE] : 7
diff --git a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.sl b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.sl
index 23bd568..40c1a67 100644
--- a/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.sl
+++ b/third_party/tests/YosysOldTests/usb_phy/YosysOldUsb.sl
@@ -1 +1 @@
- -writepp -parse -mt max -nopython -fileunit */*.v +incdir+. -nobuiltin -nocache
+ -writepp -parse -mt max rtl/usb_phy.v rtl/usb_rx_phy.v rtl/usb_tx_phy.v +incdir+.+./rtl
