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| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| [INFO :CM0023] Creating log file ./slpp_all/surelog.log. |
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| [WARNI:CM0010] Command line argument "-full64" ignored. |
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| [WARNI:CM0010] Command line argument "-PP" ignored. |
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| [WARNI:CM0010] Command line argument "-notice" ignored. |
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| [WARNI:CM0010] Command line argument "-line" ignored. |
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| [NOTE :CM0009] Command line argument "+lint=all,noVCDE,noUI" ignored. |
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| [NOTE :CM0009] Command line argument "+v2k" ignored. |
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| [WARNI:CM0010] Command line argument "-quiet" ignored. |
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| [WARNI:CM0010] Command line argument "-debug_pp" ignored. |
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| [WARNI:CM0010] Command line argument "-Mdirectory=sim/csrc" ignored. |
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| [NOTE :CM0009] Command line argument "+vc+list" ignored. |
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| [WARNI:CM0010] Command line argument "-CC" ignored. |
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| [WARNI:CM0010] Command line argument "-std=c++11" ignored. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [WARNI:CM0005] Include path "/include" does not exist. |
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| [NOTE :PP0105] src/main/verilog/vscale_ctrl_constants.vh:42 Multiply defined macro "MEM_TYPE_WIDTH", |
| src/main/verilog/vscale_ctrl_constants.vh:33 previous definition. |
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| [INFO :CM0029] Using global timescale: "1ns/10ps". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] src/main/verilog/vscale_PC_mux.v:5 Compile module "work@vscale_PC_mux". |
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| [INFO :CP0303] src/main/verilog/vscale_alu.v:5 Compile module "work@vscale_alu". |
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| [INFO :CP0303] src/main/verilog/vscale_core.v:5 Compile module "work@vscale_core". |
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| [INFO :CP0303] src/main/verilog/vscale_csr_file.v:5 Compile module "work@vscale_csr_file". |
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| [INFO :CP0303] src/main/verilog/vscale_ctrl.v:6 Compile module "work@vscale_ctrl". |
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| [INFO :CP0303] src/test/verilog/vscale_dp_hasti_sram.v:2 Compile module "work@vscale_dp_hasti_sram". |
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| [INFO :CP0303] src/main/verilog/vscale_hasti_bridge.v:4 Compile module "work@vscale_hasti_bridge". |
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| [INFO :CP0303] src/test/verilog/vscale_hex_tb.v:3 Compile module "work@vscale_hex_tb". |
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| [INFO :CP0303] src/main/verilog/vscale_imm_gen.v:5 Compile module "work@vscale_imm_gen". |
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| [INFO :CP0303] src/main/verilog/vscale_mul_div.v:4 Compile module "work@vscale_mul_div". |
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| [INFO :CP0303] src/main/verilog/vscale_pipeline.v:7 Compile module "work@vscale_pipeline". |
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| [INFO :CP0303] src/main/verilog/vscale_regfile.v:2 Compile module "work@vscale_regfile". |
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| [INFO :CP0303] src/test/verilog/vscale_sim_top.v:4 Compile module "work@vscale_sim_top". |
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| [INFO :CP0303] src/main/verilog/vscale_src_a_mux.v:5 Compile module "work@vscale_src_a_mux". |
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| [INFO :CP0303] src/main/verilog/vscale_src_b_mux.v:5 Compile module "work@vscale_src_b_mux". |
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| [INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox". |
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| [INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process". |
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| [INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore". |
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| [NOTE :CP0309] src/main/verilog/vscale_PC_mux.v:13 Implicit port type (wire) for "PC_PIF". |
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| [NOTE :CP0309] src/main/verilog/vscale_core.v:10 Implicit port type (wire) for "imem_haddr", |
| there are 22 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_csr_file.v:15 Implicit port type (wire) for "illegal_access", |
| there are 6 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_ctrl.v:20 Implicit port type (wire) for "bypass_rs1", |
| there are 3 more instances of this message. |
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| [NOTE :CP0309] src/test/verilog/vscale_dp_hasti_sram.v:15 Implicit port type (wire) for "p0_hrdata", |
| there are 5 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_hasti_bridge.v:5 Implicit port type (wire) for "haddr", |
| there are 10 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_mul_div.v:8 Implicit port type (wire) for "req_ready", |
| there are 2 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_pipeline.v:14 Implicit port type (wire) for "imem_addr", |
| there are 8 more instances of this message. |
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| [NOTE :CP0309] src/main/verilog/vscale_regfile.v:7 Implicit port type (wire) for "rd1", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] src/test/verilog/vscale_sim_top.v:8 Implicit port type (wire) for "htif_pcr_req_ready", |
| there are 2 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] src/test/verilog/vscale_hex_tb.v:3 Top level module "work@vscale_hex_tb". |
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| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 5. |
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| [NOTE :EL0510] Nb instances: 16. |
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| [NOTE :EL0511] Nb leaf instances: 2. |
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| [ FATAL] : 0 |
| [ ERROR] : 0 |
| [WARNING] : 10 |
| [ NOTE] : 19 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
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| 3.10user 0.06system 0:03.24elapsed 97%CPU (0avgtext+0avgdata 104300maxresident)k |
| 288inputs+2808outputs (0major+28335minor)pagefaults 0swaps |
