SVIncCompil/Testcases/SimpleParserTest/SimpleParserTestCache_diff.log

Test cache capabilities (rerun)
********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

********************************************
*  SURELOG System Verilog Compiler/Linter  *
********************************************

[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[WARNI:PA0205] arbiter.inc:6 No timescale set for "arbiter".

[WARNI:PA0205] arbiter_tb.v:2 No timescale set for "top".

[WARNI:PA0205] encoder.v:7 No timescale set for "encoder_using_case".

[WARNI:PA0205] jkff_udp.v:7 No timescale set for "jkff_udp".

[WARNI:PA0205] jkff_udp.v:24 No timescale set for "xor2_input".

[WARNI:PA0205] dff.v:8 No timescale set for "dff_async_reset".

[WARNI:PA0205] m_input_mult.v:2 No timescale set for "case1".

[WARNI:PA0205] m_input_mult.v:21 No timescale set for "case2".

[WARNI:PA0205] m_input_mult.v:49 No timescale set for "pri_encooder".

[WARNI:PA0205] uart.v:8 No timescale set for "uart".

[WARNI:PA0205] full_adder.v:7 No timescale set for "full_adder_gates".

[WARNI:PA0205] lfsr_task.v:2 No timescale set for "LFSR_TASK".

[WARNI:PA0205] mux21.v:7 No timescale set for "mux21_switch".

[WARNI:PA0205] synfifo.v:8 No timescale set for "syn_fifo".

[INFO :CP0300] Compilation...

[INFO :CP0303] arbiter.inc:6 Compile module "work@arbiter".

[INFO :CP0303] lfsr_task.v:2 Compile module "work@LFSR_TASK".

[INFO :CP0303] m_input_mult.v:21 Compile module "work@case2".

[INFO :CP0303] encoder.v:7 Compile module "work@encoder_using_case".

[INFO :CP0303] dff.v:8 Compile module "work@dff_async_reset".

[INFO :CP0305] jkff_udp.v:7 Compile udp "work@jkff_udp".

[INFO :CP0303] m_input_mult.v:49 Compile module "work@pri_encooder".

[INFO :CP0303] mux21.v:7 Compile module "work@mux21_switch".

[INFO :CP0303] arbiter_tb.v:2 Compile module "work@top".

[INFO :CP0305] jkff_udp.v:24 Compile udp "work@xor2_input".

[INFO :CP0303] uart.v:8 Compile module "work@uart".

[INFO :CP0303] m_input_mult.v:2 Compile module "work@case1".

[INFO :CP0303] full_adder.v:7 Compile module "work@full_adder_gates".

[INFO :CP0303] synfifo.v:8 Compile module "work@syn_fifo".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".

[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".

[WARNI:CP0310] lfsr_task.v:2 Port "Reset" definition missing its direction (input, output, inout),
there are 1 more instances of this message.

[NOTE :CP0309] mux21.v:7 Implicit port type (wire) for "out".

[NOTE :CP0309] arbiter.inc:13 Implicit port type (wire) for "gnt3",
there are 3 more instances of this message.

[NOTE :CP0309] m_input_mult.v:49 Implicit port type (wire) for "Sel",
there are 1 more instances of this message.

[NOTE :CP0309] m_input_mult.v:2 Implicit port type (wire) for "out2".

[NOTE :CP0309] full_adder.v:7 Implicit port type (wire) for "sum",
there are 1 more instances of this message.

[NOTE :CP0309] synfifo.v:17 Implicit port type (wire) for "empty",
there are 1 more instances of this message.

[NOTE :CP0309] m_input_mult.v:21 Implicit port type (wire) for "out2".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] arbiter_tb.v:2 Top level module "work@top".

[NOTE :EL0503] encoder.v:7 Top level module "work@encoder_using_case".

[NOTE :EL0503] dff.v:8 Top level module "work@dff_async_reset".

[NOTE :EL0503] m_input_mult.v:2 Top level module "work@case1".

[NOTE :EL0503] m_input_mult.v:21 Top level module "work@case2".

[NOTE :EL0503] m_input_mult.v:49 Top level module "work@pri_encooder".

[NOTE :EL0503] uart.v:8 Top level module "work@uart".

[NOTE :EL0503] full_adder.v:7 Top level module "work@full_adder_gates".

[NOTE :EL0503] lfsr_task.v:2 Top level module "work@LFSR_TASK".

[NOTE :EL0503] mux21.v:7 Top level module "work@mux21_switch".

[NOTE :EL0503] synfifo.v:8 Top level module "work@syn_fifo".

[WARNI:EL0505] another_arbiter.v:2 Multiply defined module "work@arbiter",
               arbiter.inc:6 previous definition.

[WARNI:EL0505] encoder_case.v:8 Multiply defined module "work@encoder_using_case",
               encoder.v:7 previous definition.

[NOTE :EL0504] Multiple top level modules in design.

[WARNI:EL0500] synfifo.v:91 Cannot find a module definition for "work@syn_fifo::ram_dp_ar_aw".

[NOTE :EL0508] Nb Top level modules: 11.

[NOTE :EL0509] Max instance depth: 2.

[NOTE :EL0510] Nb instances: 20.

[NOTE :EL0511] Nb leaf instances: 10.

[WARNI:EL0512] Nb undefined modules: 1.

[WARNI:EL0513] Nb undefined instances: 1.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 20
[   NOTE] : 23

********************************************
*   End SURELOG SVerilog Compiler/Linter   *
********************************************


real	0m1.536s
user	0m4.341s
sys	0m0.072s

real	0m0.162s
user	0m0.138s
sys	0m0.022s
4.48user 0.09system 0:01.70elapsed 269%CPU (0avgtext+0avgdata 86484maxresident)k
0inputs+1000outputs (0major+34460minor)pagefaults 0swaps