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foss-fpga-tools
/
third_party
/
Surelog
/
refs/heads/mithro-patch-1
/
.
/
SVIncCompil
/
Testcases
/
UtdSV
/
generate.v
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module
tb_generate
;
genvar i
;
generate
for
(
i
=
0
;
i
<
4
;
i
=
i
+
1
)
begin
:
MEM
memory U
(
read
,
write
,
data_in
[(
i
*
8
)+
7
:(
i
*
8
)],
address
,
data_out
[(
i
*
8
)+
7
:(
i
*
8
)]);
end
endgenerate
endmodule
