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foss-fpga-tools
/
third_party
/
Surelog
/
refs/heads/mithro-patch-1
/
.
/
SVIncCompil
/
Testcases
/
UtdSV
/
loops.v
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module
tb_loops
;
integer a
=
0
;
initial
begin
while
(
a
<
10
)
begin
a
=
a
+
1
;
end
wait
(
10
);
forever
begin
a
=
a
-
1
;
if
(
a
<
0
)
$finish
;
end
end
endmodule