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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
t_multitop1s s ();
initial $display("In '%m'");
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule