| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [ERROR:PP0107] rtl/lm32_dcache.v:118 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_dcache.v:119 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_dcache.v:129 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_dtlb.v:89 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_dtlb.v:90 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_icache.v:128 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_icache.v:129 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_icache.v:139 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_instruction_unit.v:196 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_itlb.v:88 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_itlb.v:89 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [ERROR:PP0107] rtl/lm32_load_store_unit.v:159 Too many arguments (1) for macro "CLOG2", |
| ./rtl/lm32_config.v:57 macro definition takes 0. |
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| [WARNI:PA0205] rtl/lm32_adder.v:55 No timescale set for "lm32_adder". |
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| [WARNI:PA0205] rtl/lm32_addsub.v:54 No timescale set for "lm32_addsub". |
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| [WARNI:PA0205] rtl/lm32_cpu.v:98 No timescale set for "lm32_cpu". |
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| [WARNI:PA0205] rtl/lm32_dcache.v:62 No timescale set for "lm32_dcache". |
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| [WARNI:PA0205] rtl/lm32_debug.v:61 No timescale set for "lm32_debug". |
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| [WARNI:PA0205] rtl/lm32_decoder.v:65 No timescale set for "lm32_decoder". |
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| [WARNI:PA0205] rtl/lm32_dp_ram.v:36 No timescale set for "lm32_dp_ram". |
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| [WARNI:PA0205] rtl/lm32_dtlb.v:41 No timescale set for "lm32_dtlb". |
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| [WARNI:PA0205] rtl/lm32_icache.v:67 No timescale set for "lm32_icache". |
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| [WARNI:PA0205] rtl/lm32_instruction_unit.v:76 No timescale set for "lm32_instruction_unit". |
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| [WARNI:PA0205] rtl/lm32_interrupt.v:55 No timescale set for "lm32_interrupt". |
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| [WARNI:PA0205] rtl/lm32_itlb.v:40 No timescale set for "lm32_itlb". |
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| [WARNI:PA0205] rtl/lm32_load_store_unit.v:68 No timescale set for "lm32_load_store_unit". |
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| [WARNI:PA0205] rtl/lm32_logic_op.v:55 No timescale set for "lm32_logic_op". |
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| [WARNI:PA0205] rtl/lm32_mc_arithmetic.v:56 No timescale set for "lm32_mc_arithmetic". |
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| [WARNI:PA0205] rtl/lm32_multiplier.v:55 No timescale set for "lm32_multiplier". |
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| [WARNI:PA0205] rtl/lm32_ram.v:60 No timescale set for "lm32_ram". |
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| [WARNI:PA0205] rtl/lm32_shifter.v:55 No timescale set for "lm32_shifter". |
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| [WARNI:PA0205] rtl/lm32_top.v:55 No timescale set for "lm32_top". |
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| [WARNI:PA0205] sim/tb_lm32_system.v:33 No timescale set for "testbench". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] rtl/lm32_adder.v:55 Compile module "work@lm32_adder". |
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| [INFO :CP0303] rtl/lm32_addsub.v:54 Compile module "work@lm32_addsub". |
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| [INFO :CP0303] rtl/lm32_cpu.v:98 Compile module "work@lm32_cpu". |
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| [INFO :CP0303] rtl/lm32_dcache.v:62 Compile module "work@lm32_dcache". |
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| [INFO :CP0303] rtl/lm32_debug.v:61 Compile module "work@lm32_debug". |
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| [INFO :CP0303] rtl/lm32_decoder.v:65 Compile module "work@lm32_decoder". |
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| [INFO :CP0303] rtl/lm32_dp_ram.v:36 Compile module "work@lm32_dp_ram". |
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| [INFO :CP0303] rtl/lm32_dtlb.v:41 Compile module "work@lm32_dtlb". |
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| [INFO :CP0303] rtl/lm32_icache.v:67 Compile module "work@lm32_icache". |
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| [INFO :CP0303] rtl/lm32_instruction_unit.v:76 Compile module "work@lm32_instruction_unit". |
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| [INFO :CP0303] rtl/lm32_interrupt.v:55 Compile module "work@lm32_interrupt". |
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| [INFO :CP0303] rtl/lm32_itlb.v:40 Compile module "work@lm32_itlb". |
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| [INFO :CP0303] rtl/lm32_load_store_unit.v:68 Compile module "work@lm32_load_store_unit". |
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| [INFO :CP0303] rtl/lm32_logic_op.v:55 Compile module "work@lm32_logic_op". |
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| [INFO :CP0303] rtl/lm32_mc_arithmetic.v:56 Compile module "work@lm32_mc_arithmetic". |
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| [INFO :CP0303] rtl/lm32_multiplier.v:55 Compile module "work@lm32_multiplier". |
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| [INFO :CP0303] rtl/lm32_ram.v:60 Compile module "work@lm32_ram". |
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| [INFO :CP0303] rtl/lm32_shifter.v:55 Compile module "work@lm32_shifter". |
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| [INFO :CP0303] rtl/lm32_top.v:55 Compile module "work@lm32_top". |
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| [INFO :CP0303] sim/tb_lm32_system.v:33 Compile module "work@testbench". |
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| [NOTE :CP0309] rtl/lm32_adder.v:62 Implicit port type (wire) for "adder_result_x", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_addsub.v:61 Implicit port type (wire) for "Result", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_cpu.v:118 Implicit port type (wire) for "I_DAT_O", |
| there are 17 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_dcache.v:80 Implicit port type (wire) for "stall_request", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_debug.v:81 Implicit port type (wire) for "bp_match", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_decoder.v:80 Implicit port type (wire) for "x_bypass_enable", |
| there are 28 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_dp_ram.v:49 Implicit port type (wire) for "do_a", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_dtlb.v:62 Implicit port type (wire) for "physical_load_store_address_m", |
| there are 5 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_icache.v:83 Implicit port type (wire) for "stall_request", |
| there are 2 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_instruction_unit.v:116 Implicit port type (wire) for "icache_stall_request", |
| there are 11 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_interrupt.v:71 Implicit port type (wire) for "interrupt_exception". |
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| [NOTE :CP0309] rtl/lm32_itlb.v:60 Implicit port type (wire) for "stall_request", |
| there are 2 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_load_store_unit.v:106 Implicit port type (wire) for "dcache_refill_request", |
| there are 8 more instances of this message. |
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| [NOTE :CP0309] rtl/lm32_mc_arithmetic.v:69 Implicit port type (wire) for "stall_request_x". |
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| [NOTE :CP0309] rtl/lm32_ram.v:72 Implicit port type (wire) for "read_data". |
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| [NOTE :CP0309] rtl/lm32_shifter.v:65 Implicit port type (wire) for "shifter_result_m". |
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| [NOTE :CP0309] rtl/lm32_top.v:75 Implicit port type (wire) for "I_DAT_O", |
| there are 17 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] rtl/lm32_dp_ram.v:36 Top level module "work@lm32_dp_ram". |
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| [NOTE :EL0503] sim/tb_lm32_system.v:33 Top level module "work@testbench". |
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| [NOTE :EL0504] Multiple top level modules in design. |
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| [NOTE :EL0508] Nb Top level modules: 2. |
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| [NOTE :EL0509] Max instance depth: 8. |
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| [NOTE :EL0510] Nb instances: 27. |
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| [NOTE :EL0511] Nb leaf instances: 10. |
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| [ FATAL] : 0 |
| [ ERROR] : 12 |
| [WARNING] : 20 |
| [ NOTE] : 24 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 8.70user 0.14system 0:08.87elapsed 99%CPU (0avgtext+0avgdata 266640maxresident)k |
| 776inputs+800outputs (0major+64046minor)pagefaults 0swaps |
