blob: 2978d3dd976ff66f0bd420441fb118e41d96e675 [file] [log] [blame] [edit]
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* SURELOG System Verilog Compiler/Linter *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
[INFO :CM0024] Executing with 4 threads.
[INFO :CM0020] Separate compilation-unit mode is on.
[WARNI:PA0200] Cannot split large file "cam_bram_top.v".
[INFO :CP0300] Compilation...
[INFO :CP0303] cam_bram.vh:32 Compile module "work@cam_bram".
[INFO :CP0303] cam_bram_top.v:32 Compile module "work@cam_bram_top".
[INFO :CP0303] cam_srl_top.v:32 Compile module "work@cam_srl_top".
[INFO :CP0303] cam_srl.vh:32 Compile module "work@cam_srl".
[INFO :CP0303] ram_dp.vh:32 Compile module "work@ram_dp".
[INFO :CP0303] priority_encoder.vh:32 Compile module "work@priority_encoder".
[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:4 Compile class "work@mailbox".
[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:33 Compile class "work@process".
[INFO :CP0302] /home/alain/Surelog/SVIncCompil/dist/surelog/bin/../sv/builtin.sv:58 Compile class "work@semaphore".
[INFO :EL0526] Design Elaboration...
[NOTE :EL0503] cam_srl_top.v:32 Top level module "work@cam_srl_top".
[NOTE :EL0503] cam_bram_top.v:32 Top level module "work@cam_bram_top".
[NOTE :EL0504] Multiple top level modules in design.
[NOTE :EL0508] Nb Top level modules: 2.
[NOTE :EL0509] Max instance depth: 4.
[NOTE :EL0510] Nb instances: 6.
[NOTE :EL0511] Nb leaf instances: 0.
[ FATAL] : 0
[ ERROR] : 0
[WARNING] : 1
[ NOTE] : 7
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* End SURELOG SVerilog Compiler/Linter *
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3.36user 0.06system 0:01.76elapsed 194%CPU (0avgtext+0avgdata 66516maxresident)k
8inputs+696outputs (0major+14270minor)pagefaults 0swaps