SVIncCompil/Testcases/YosysOldTests/YosysOldI2c_diff.log

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*  SURELOG System Verilog Compiler/Linter  *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.

[INFO :CM0024] Executing with 4 threads.

[INFO :CM0020] Separate compilation-unit mode is on.

[WARNI:PA0205] scripts/sim_mul.v:2 No timescale set for "$mul".

[WARNI:PA0205] scripts/sim_stdcells.v:28 No timescale set for "$_INV_".

[WARNI:PA0205] scripts/sim_stdcells.v:34 No timescale set for "$_AND_".

[WARNI:PA0205] scripts/sim_stdcells.v:40 No timescale set for "$_OR_".

[WARNI:PA0205] scripts/sim_stdcells.v:46 No timescale set for "$_XOR_".

[WARNI:PA0205] scripts/sim_stdcells.v:52 No timescale set for "$_MUX_".

[WARNI:PA0205] scripts/sim_stdcells.v:63 No timescale set for "$_DFF_N_".

[WARNI:PA0205] scripts/sim_stdcells.v:71 No timescale set for "$_DFF_P_".

[WARNI:PA0205] scripts/sim_stdcells.v:79 No timescale set for "$_DFF_NN0_".

[WARNI:PA0205] scripts/sim_stdcells.v:90 No timescale set for "$_DFF_NN1_".

[WARNI:PA0205] scripts/sim_stdcells.v:101 No timescale set for "$_DFF_NP0_".

[WARNI:PA0205] scripts/sim_stdcells.v:112 No timescale set for "$_DFF_NP1_".

[WARNI:PA0205] scripts/sim_stdcells.v:123 No timescale set for "$_DFF_PN0_".

[WARNI:PA0205] scripts/sim_stdcells.v:134 No timescale set for "$_DFF_PN1_".

[WARNI:PA0205] scripts/sim_stdcells.v:145 No timescale set for "$_DFF_PP0_".

[WARNI:PA0205] scripts/sim_stdcells.v:156 No timescale set for "$_DFF_PP1_".

[INFO :CP0300] Compilation...

[INFO :CP0303] scripts/sim_stdcells.v:34 Compile module "work@$_AND_".

[INFO :CP0303] scripts/sim_stdcells.v:79 Compile module "work@$_DFF_NN0_".

[INFO :CP0303] scripts/sim_stdcells.v:90 Compile module "work@$_DFF_NN1_".

[INFO :CP0303] scripts/sim_stdcells.v:112 Compile module "work@$_DFF_NP1_".

[INFO :CP0303] scripts/sim_stdcells.v:101 Compile module "work@$_DFF_NP0_".

[INFO :CP0303] scripts/sim_stdcells.v:63 Compile module "work@$_DFF_N_".

[INFO :CP0303] scripts/sim_stdcells.v:123 Compile module "work@$_DFF_PN0_".

[INFO :CP0303] scripts/sim_stdcells.v:145 Compile module "work@$_DFF_PP0_".

[INFO :CP0303] scripts/sim_stdcells.v:134 Compile module "work@$_DFF_PN1_".

[INFO :CP0303] scripts/sim_stdcells.v:156 Compile module "work@$_DFF_PP1_".

[INFO :CP0303] scripts/sim_stdcells.v:28 Compile module "work@$_INV_".

[INFO :CP0303] scripts/sim_stdcells.v:40 Compile module "work@$_OR_".

[INFO :CP0303] scripts/sim_mul.v:2 Compile module "work@$mul".

[INFO :CP0303] scripts/sim_stdcells.v:71 Compile module "work@$_DFF_P_".

[INFO :CP0303] scripts/sim_stdcells.v:52 Compile module "work@$_MUX_".

[INFO :CP0303] scripts/sim_stdcells.v:46 Compile module "work@$_XOR_".

[NOTE :CP0309] scripts/sim_stdcells.v:34 Implicit port type (wire) for "Y".

[NOTE :CP0309] scripts/sim_stdcells.v:40 Implicit port type (wire) for "Y".

[NOTE :CP0309] scripts/sim_stdcells.v:46 Implicit port type (wire) for "Y".

[NOTE :CP0309] scripts/sim_stdcells.v:28 Implicit port type (wire) for "Y".

[NOTE :CP0309] scripts/sim_mul.v:2 Implicit port type (wire) for "Y".

[INFO :EL0526] Design Elaboration...

[NOTE :EL0503] scripts/sim_mul.v:2 Top level module "work@$mul".

[NOTE :EL0503] scripts/sim_stdcells.v:28 Top level module "work@$_INV_".

[NOTE :EL0503] scripts/sim_stdcells.v:34 Top level module "work@$_AND_".

[NOTE :EL0503] scripts/sim_stdcells.v:40 Top level module "work@$_OR_".

[NOTE :EL0503] scripts/sim_stdcells.v:46 Top level module "work@$_XOR_".

[NOTE :EL0503] scripts/sim_stdcells.v:52 Top level module "work@$_MUX_".

[NOTE :EL0503] scripts/sim_stdcells.v:63 Top level module "work@$_DFF_N_".

[NOTE :EL0503] scripts/sim_stdcells.v:71 Top level module "work@$_DFF_P_".

[NOTE :EL0503] scripts/sim_stdcells.v:79 Top level module "work@$_DFF_NN0_".

[NOTE :EL0503] scripts/sim_stdcells.v:90 Top level module "work@$_DFF_NN1_".

[NOTE :EL0503] scripts/sim_stdcells.v:101 Top level module "work@$_DFF_NP0_".

[NOTE :EL0503] scripts/sim_stdcells.v:112 Top level module "work@$_DFF_NP1_".

[NOTE :EL0503] scripts/sim_stdcells.v:123 Top level module "work@$_DFF_PN0_".

[NOTE :EL0503] scripts/sim_stdcells.v:134 Top level module "work@$_DFF_PN1_".

[NOTE :EL0503] scripts/sim_stdcells.v:145 Top level module "work@$_DFF_PP0_".

[NOTE :EL0503] scripts/sim_stdcells.v:156 Top level module "work@$_DFF_PP1_".

[NOTE :EL0504] Multiple top level modules in design.

[NOTE :EL0508] Nb Top level modules: 16.

[NOTE :EL0509] Max instance depth: 1.

[NOTE :EL0510] Nb instances: 16.

[NOTE :EL0511] Nb leaf instances: 4.

[  FATAL] : 0
[  ERROR] : 0
[WARNING] : 16
[   NOTE] : 26

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*   End SURELOG SVerilog Compiler/Linter   *
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0.72user 0.03system 0:00.44elapsed 171%CPU (0avgtext+0avgdata 41716maxresident)k
0inputs+32outputs (0major+8154minor)pagefaults 0swaps