| |
| /-----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \-----------------------------------------------------------------------------/ |
| |
| |
| -- Executing script file `scripts/synth.ys' -- |
| |
| 1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/i2c_master_bit_ctrl.v |
| Parsing Verilog input from `rtl/i2c_master_bit_ctrl.v' to AST representation. |
| Warning: Found one of those horrible `synopsys translate_off' comments. |
| It is strongly suggested to use `ifdef constructs instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Generating RTLIL representation for module `\i2c_master_bit_ctrl'. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/i2c_master_byte_ctrl.v |
| Parsing Verilog input from `rtl/i2c_master_byte_ctrl.v' to AST representation. |
| Warning: Found one of those horrible `synopsys translate_off' comments. |
| It is strongly suggested to use `ifdef constructs instead! |
| Warning: Found one of those horrible `synopsys full_case' comments. |
| It is strongly suggested to use verilog x-values and default branches instead! |
| Warning: Found one of those horrible `synopsys parallel_case' comments. |
| It is strongly suggested to use verilog `parallel_case' attributes instead! |
| Generating RTLIL representation for module `\i2c_master_byte_ctrl'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/i2c_master_top.v |
| Parsing Verilog input from `rtl/i2c_master_top.v' to AST representation. |
| Warning: Found one of those horrible `synopsys translate_off' comments. |
| It is strongly suggested to use `ifdef constructs instead! |
| Generating RTLIL representation for module `\i2c_master_top'. |
| Successfully finished Verilog frontend. |
| |
| 4. Executing HIERARCHY pass (managing design hierarchy). |
| Full command line: hierarchy -top i2c_master_top |
| Top module: \i2c_master_top |
| Used module: \i2c_master_byte_ctrl |
| Used module: \i2c_master_bit_ctrl |
| Removed 0 unused modules. |
| Top module: \i2c_master_top |
| Used module: \i2c_master_byte_ctrl |
| Used module: \i2c_master_bit_ctrl |
| Removed 0 unused modules. |
| |
| -- Executing script file `../scripts/generic.ys' -- |
| |
| 5. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6. Executing PROC pass (convert processes to netlists). |
| |
| 6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed 1 dead cases from process $proc$rtl/i2c_master_top.v:167$67 in module \i2c_master_top. |
| Removed a total of 1 dead cases. |
| |
| 6.3. Executing PROC_ARST pass (detect async resets in processes). |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:282$22'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:295$27'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:303$30'. |
| Found async reset \nReset in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| Found async reset \nReset in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:177$50'. |
| Found async reset \nReset in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:188$52'. |
| Found async reset \nReset in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| Found async reset \rst_i in `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| Found async reset \rst_i in `\i2c_master_top.$proc$rtl/i2c_master_top.v:206$70'. |
| Found async reset \rst_i in `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| Found async reset \rst_i in `\i2c_master_top.$proc$rtl/i2c_master_top.v:289$85'. |
| |
| 6.4. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:193$1'. |
| creating decoder for signal `$0\dscl_oen[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| creating decoder for signal `$0\clk_en[0:0]'. |
| creating decoder for signal `$0\cnt[15:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| creating decoder for signal `$0\dSCL[0:0]'. |
| creating decoder for signal `$0\dSDA[0:0]'. |
| creating decoder for signal `$0\sSCL[0:0]'. |
| creating decoder for signal `$0\sSDA[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| creating decoder for signal `$0\sta_condition[0:0]'. |
| creating decoder for signal `$0\sto_condition[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:282$22'. |
| creating decoder for signal `$0\busy[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:295$27'. |
| creating decoder for signal `$0\cmd_stop[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:303$30'. |
| creating decoder for signal `$0\al[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:313$40'. |
| creating decoder for signal `$0\dout[0:0]'. |
| Creating decoders for process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| creating decoder for signal `$0\c_state[16:0]'. |
| creating decoder for signal `$0\cmd_ack[0:0]'. |
| creating decoder for signal `$0\scl_oen[0:0]'. |
| creating decoder for signal `$0\sda_chk[0:0]'. |
| creating decoder for signal `$0\sda_oen[0:0]'. |
| Creating decoders for process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:177$50'. |
| creating decoder for signal `$0\sr[7:0]'. |
| Creating decoders for process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:188$52'. |
| creating decoder for signal `$0\dcnt[2:0]'. |
| Creating decoders for process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| creating decoder for signal `$0\ack_out[0:0]'. |
| creating decoder for signal `$0\c_state[4:0]'. |
| creating decoder for signal `$0\cmd_ack[0:0]'. |
| creating decoder for signal `$0\core_cmd[3:0]'. |
| creating decoder for signal `$0\core_txd[0:0]'. |
| creating decoder for signal `$0\ld[0:0]'. |
| creating decoder for signal `$0\shift[0:0]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:163$63'. |
| creating decoder for signal `$0\wb_ack_o[0:0]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:167$67'. |
| creating decoder for signal `$0\wb_dat_o[7:0]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| creating decoder for signal `$0\ctr[7:0]'. |
| creating decoder for signal `$0\prer[15:0] [7:0]'. |
| creating decoder for signal `$0\prer[15:0] [15:8]'. |
| creating decoder for signal `$0\txr[7:0]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:206$70'. |
| creating decoder for signal `$0\cr[7:0] [2:1]'. |
| creating decoder for signal `$0\cr[7:0] [0]'. |
| creating decoder for signal `$0\cr[7:0] [7:4]'. |
| creating decoder for signal `$0\cr[7:0] [3]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| creating decoder for signal `$0\al[0:0]'. |
| creating decoder for signal `$0\irq_flag[0:0]'. |
| creating decoder for signal `$0\rxack[0:0]'. |
| creating decoder for signal `$0\tip[0:0]'. |
| Creating decoders for process `\i2c_master_top.$proc$rtl/i2c_master_top.v:289$85'. |
| creating decoder for signal `$0\wb_inta_o[0:0]'. |
| |
| 6.5. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\i2c_master_bit_ctrl.\dscl_oen' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:193$1'. |
| created $dff cell `$procdff$868' with positive edge clock. |
| Creating register for signal `\i2c_master_bit_ctrl.\clk_en' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| created $adff cell `$procdff$869' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\cnt' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| created $adff cell `$procdff$870' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\dSCL' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| created $adff cell `$procdff$871' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\dSDA' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| created $adff cell `$procdff$872' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sSCL' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| created $adff cell `$procdff$873' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sSDA' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| created $adff cell `$procdff$874' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sta_condition' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| created $adff cell `$procdff$875' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sto_condition' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| created $adff cell `$procdff$876' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\busy' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:282$22'. |
| created $adff cell `$procdff$877' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\cmd_stop' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:295$27'. |
| created $adff cell `$procdff$878' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\al' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:303$30'. |
| created $adff cell `$procdff$879' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\dout' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:313$40'. |
| created $dff cell `$procdff$880' with positive edge clock. |
| Creating register for signal `\i2c_master_bit_ctrl.\c_state' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| created $adff cell `$procdff$881' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\cmd_ack' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| created $adff cell `$procdff$882' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\scl_oen' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| created $adff cell `$procdff$883' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sda_chk' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| created $adff cell `$procdff$884' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_bit_ctrl.\sda_oen' using process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| created $adff cell `$procdff$885' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\sr' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:177$50'. |
| created $adff cell `$procdff$886' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\dcnt' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:188$52'. |
| created $adff cell `$procdff$887' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\ack_out' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$888' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\c_state' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$889' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\cmd_ack' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$890' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\core_cmd' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$891' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\core_txd' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$892' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\ld' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$893' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_byte_ctrl.\shift' using process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| created $adff cell `$procdff$894' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\wb_ack_o' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:163$63'. |
| created $dff cell `$procdff$895' with positive edge clock. |
| Creating register for signal `\i2c_master_top.\wb_dat_o' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:167$67'. |
| created $dff cell `$procdff$896' with positive edge clock. |
| Creating register for signal `\i2c_master_top.\ctr' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| created $adff cell `$procdff$897' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\prer' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| created $adff cell `$procdff$898' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\txr' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| created $adff cell `$procdff$899' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\cr' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:206$70'. |
| created $adff cell `$procdff$900' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\al' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| created $adff cell `$procdff$901' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\irq_flag' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| created $adff cell `$procdff$902' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\rxack' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| created $adff cell `$procdff$903' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\tip' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| created $adff cell `$procdff$904' with positive edge clock and negative level reset. |
| Creating register for signal `\i2c_master_top.\wb_inta_o' using process `\i2c_master_top.$proc$rtl/i2c_master_top.v:289$85'. |
| created $adff cell `$procdff$905' with positive edge clock and negative level reset. |
| |
| 6.6. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:193$1'. |
| Found and cleaned up 4 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:200$4'. |
| Found and cleaned up 2 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:236$12'. |
| Found and cleaned up 2 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:264$14'. |
| Found and cleaned up 2 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:282$22'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:282$22'. |
| Found and cleaned up 3 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:295$27'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:295$27'. |
| Found and cleaned up 2 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:303$30'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:303$30'. |
| Found and cleaned up 1 empty switch in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:313$40'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:313$40'. |
| Found and cleaned up 5 empty switches in `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| Removing empty process `\i2c_master_bit_ctrl.$proc$rtl/i2c_master_bit_ctrl.v:339$43'. |
| Found and cleaned up 4 empty switches in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:177$50'. |
| Removing empty process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:177$50'. |
| Found and cleaned up 4 empty switches in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:188$52'. |
| Removing empty process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:188$52'. |
| Found and cleaned up 16 empty switches in `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| Removing empty process `\i2c_master_byte_ctrl.$proc$rtl/i2c_master_byte_ctrl.v:205$57'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:163$63'. |
| Found and cleaned up 1 empty switch in `\i2c_master_top.$proc$rtl/i2c_master_top.v:167$67'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:167$67'. |
| Found and cleaned up 4 empty switches in `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:182$68'. |
| Found and cleaned up 5 empty switches in `\i2c_master_top.$proc$rtl/i2c_master_top.v:206$70'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:206$70'. |
| Found and cleaned up 2 empty switches in `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:265$75'. |
| Found and cleaned up 2 empty switches in `\i2c_master_top.$proc$rtl/i2c_master_top.v:289$85'. |
| Removing empty process `\i2c_master_top.$proc$rtl/i2c_master_top.v:289$85'. |
| Cleaned up 59 empty switches. |
| |
| 7. Executing OPT pass (performing simple optimizations). |
| |
| 7.1. Optimizing in-memory representation of design. |
| |
| 7.2. Executing OPT_CONST pass (perform const folding). |
| |
| 7.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Cell `$logic_not$rtl/i2c_master_bit_ctrl.v:340$44' is identical to cell `$logic_not$rtl/i2c_master_bit_ctrl.v:283$23'. |
| Redirecting output \Y: $logic_not$rtl/i2c_master_bit_ctrl.v:340$44_Y = $logic_not$rtl/i2c_master_bit_ctrl.v:283$23_Y |
| Removing $logic_not cell `$logic_not$rtl/i2c_master_bit_ctrl.v:340$44' from module `\i2c_master_bit_ctrl'. |
| Cell `$not$rtl/i2c_master_bit_ctrl.v:237$13' is identical to cell `$not$rtl/i2c_master_bit_ctrl.v:201$5'. |
| Redirecting output \Y: $not$rtl/i2c_master_bit_ctrl.v:237$13_Y = $not$rtl/i2c_master_bit_ctrl.v:201$5_Y |
| Removing $not cell `$not$rtl/i2c_master_bit_ctrl.v:237$13' from module `\i2c_master_bit_ctrl'. |
| Cell `$not$rtl/i2c_master_bit_ctrl.v:265$15' is identical to cell `$not$rtl/i2c_master_bit_ctrl.v:201$5'. |
| Redirecting output \Y: $not$rtl/i2c_master_bit_ctrl.v:265$15_Y = $not$rtl/i2c_master_bit_ctrl.v:201$5_Y |
| Removing $not cell `$not$rtl/i2c_master_bit_ctrl.v:265$15' from module `\i2c_master_bit_ctrl'. |
| Cell `$not$rtl/i2c_master_bit_ctrl.v:296$28' is identical to cell `$not$rtl/i2c_master_bit_ctrl.v:201$5'. |
| Redirecting output \Y: $not$rtl/i2c_master_bit_ctrl.v:296$28_Y = $not$rtl/i2c_master_bit_ctrl.v:201$5_Y |
| Removing $not cell `$not$rtl/i2c_master_bit_ctrl.v:296$28' from module `\i2c_master_bit_ctrl'. |
| Cell `$not$rtl/i2c_master_bit_ctrl.v:304$31' is identical to cell `$not$rtl/i2c_master_bit_ctrl.v:201$5'. |
| Redirecting output \Y: $not$rtl/i2c_master_bit_ctrl.v:304$31_Y = $not$rtl/i2c_master_bit_ctrl.v:201$5_Y |
| Removing $not cell `$not$rtl/i2c_master_bit_ctrl.v:304$31' from module `\i2c_master_bit_ctrl'. |
| Cell `$not$rtl/i2c_master_bit_ctrl.v:309$32' is identical to cell `$not$rtl/i2c_master_bit_ctrl.v:277$16'. |
| Redirecting output \Y: $not$rtl/i2c_master_bit_ctrl.v:309$32_Y = $not$rtl/i2c_master_bit_ctrl.v:277$16_Y |
| Removing $not cell `$not$rtl/i2c_master_bit_ctrl.v:309$32' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$190_CMP0' is identical to cell `$eq$rtl/i2c_master_bit_ctrl.v:301$29'. |
| Redirecting output \Y: $procmux$190_CMP = $eq$rtl/i2c_master_bit_ctrl.v:301$29_Y |
| Removing $eq cell `$procmux$190_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$204_CMP0' is identical to cell `$procmux$153_CMP0'. |
| Redirecting output \Y: $procmux$204_CMP = $procmux$153_CMP |
| Removing $eq cell `$procmux$204_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$206_CMP0' is identical to cell `$procmux$155_CMP0'. |
| Redirecting output \Y: $procmux$206_CMP = $procmux$155_CMP |
| Removing $eq cell `$procmux$206_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$208_CMP0' is identical to cell `$procmux$157_CMP0'. |
| Redirecting output \Y: $procmux$208_CMP = $procmux$157_CMP |
| Removing $eq cell `$procmux$208_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$210_CMP0' is identical to cell `$procmux$159_CMP0'. |
| Redirecting output \Y: $procmux$210_CMP = $procmux$159_CMP |
| Removing $eq cell `$procmux$210_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$212_CMP0' is identical to cell `$procmux$161_CMP0'. |
| Redirecting output \Y: $procmux$212_CMP = $procmux$161_CMP |
| Removing $eq cell `$procmux$212_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$214_CMP0' is identical to cell `$procmux$163_CMP0'. |
| Redirecting output \Y: $procmux$214_CMP = $procmux$163_CMP |
| Removing $eq cell `$procmux$214_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$216_CMP0' is identical to cell `$procmux$165_CMP0'. |
| Redirecting output \Y: $procmux$216_CMP = $procmux$165_CMP |
| Removing $eq cell `$procmux$216_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$218_CMP0' is identical to cell `$procmux$167_CMP0'. |
| Redirecting output \Y: $procmux$218_CMP = $procmux$167_CMP |
| Removing $eq cell `$procmux$218_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$220_CMP0' is identical to cell `$procmux$169_CMP0'. |
| Redirecting output \Y: $procmux$220_CMP = $procmux$169_CMP |
| Removing $eq cell `$procmux$220_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$222_CMP0' is identical to cell `$procmux$171_CMP0'. |
| Redirecting output \Y: $procmux$222_CMP = $procmux$171_CMP |
| Removing $eq cell `$procmux$222_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$224_CMP0' is identical to cell `$procmux$173_CMP0'. |
| Redirecting output \Y: $procmux$224_CMP = $procmux$173_CMP |
| Removing $eq cell `$procmux$224_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$226_CMP0' is identical to cell `$procmux$175_CMP0'. |
| Redirecting output \Y: $procmux$226_CMP = $procmux$175_CMP |
| Removing $eq cell `$procmux$226_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$228_CMP0' is identical to cell `$procmux$177_CMP0'. |
| Redirecting output \Y: $procmux$228_CMP = $procmux$177_CMP |
| Removing $eq cell `$procmux$228_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$230_CMP0' is identical to cell `$procmux$179_CMP0'. |
| Redirecting output \Y: $procmux$230_CMP = $procmux$179_CMP |
| Removing $eq cell `$procmux$230_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$232_CMP0' is identical to cell `$procmux$181_CMP0'. |
| Redirecting output \Y: $procmux$232_CMP = $procmux$181_CMP |
| Removing $eq cell `$procmux$232_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$234_CMP0' is identical to cell `$procmux$183_CMP0'. |
| Redirecting output \Y: $procmux$234_CMP = $procmux$183_CMP |
| Removing $eq cell `$procmux$234_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$241_CMP0' is identical to cell `$procmux$194_CMP0'. |
| Redirecting output \Y: $procmux$241_CMP = $procmux$194_CMP |
| Removing $eq cell `$procmux$241_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$251_CMP0' is identical to cell `$procmux$153_CMP0'. |
| Redirecting output \Y: $procmux$251_CMP = $procmux$153_CMP |
| Removing $eq cell `$procmux$251_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$253_CMP0' is identical to cell `$procmux$155_CMP0'. |
| Redirecting output \Y: $procmux$253_CMP = $procmux$155_CMP |
| Removing $eq cell `$procmux$253_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$255_CMP0' is identical to cell `$procmux$157_CMP0'. |
| Redirecting output \Y: $procmux$255_CMP = $procmux$157_CMP |
| Removing $eq cell `$procmux$255_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$257_CMP0' is identical to cell `$procmux$159_CMP0'. |
| Redirecting output \Y: $procmux$257_CMP = $procmux$159_CMP |
| Removing $eq cell `$procmux$257_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$259_CMP0' is identical to cell `$procmux$161_CMP0'. |
| Redirecting output \Y: $procmux$259_CMP = $procmux$161_CMP |
| Removing $eq cell `$procmux$259_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$261_CMP0' is identical to cell `$procmux$163_CMP0'. |
| Redirecting output \Y: $procmux$261_CMP = $procmux$163_CMP |
| Removing $eq cell `$procmux$261_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$263_CMP0' is identical to cell `$procmux$165_CMP0'. |
| Redirecting output \Y: $procmux$263_CMP = $procmux$165_CMP |
| Removing $eq cell `$procmux$263_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$265_CMP0' is identical to cell `$procmux$167_CMP0'. |
| Redirecting output \Y: $procmux$265_CMP = $procmux$167_CMP |
| Removing $eq cell `$procmux$265_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$267_CMP0' is identical to cell `$procmux$169_CMP0'. |
| Redirecting output \Y: $procmux$267_CMP = $procmux$169_CMP |
| Removing $eq cell `$procmux$267_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$269_CMP0' is identical to cell `$procmux$171_CMP0'. |
| Redirecting output \Y: $procmux$269_CMP = $procmux$171_CMP |
| Removing $eq cell `$procmux$269_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$271_CMP0' is identical to cell `$procmux$173_CMP0'. |
| Redirecting output \Y: $procmux$271_CMP = $procmux$173_CMP |
| Removing $eq cell `$procmux$271_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$273_CMP0' is identical to cell `$procmux$175_CMP0'. |
| Redirecting output \Y: $procmux$273_CMP = $procmux$175_CMP |
| Removing $eq cell `$procmux$273_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$275_CMP0' is identical to cell `$procmux$177_CMP0'. |
| Redirecting output \Y: $procmux$275_CMP = $procmux$177_CMP |
| Removing $eq cell `$procmux$275_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$277_CMP0' is identical to cell `$procmux$179_CMP0'. |
| Redirecting output \Y: $procmux$277_CMP = $procmux$179_CMP |
| Removing $eq cell `$procmux$277_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$279_CMP0' is identical to cell `$procmux$181_CMP0'. |
| Redirecting output \Y: $procmux$279_CMP = $procmux$181_CMP |
| Removing $eq cell `$procmux$279_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$281_CMP0' is identical to cell `$procmux$183_CMP0'. |
| Redirecting output \Y: $procmux$281_CMP = $procmux$183_CMP |
| Removing $eq cell `$procmux$281_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$288_CMP0' is identical to cell `$procmux$194_CMP0'. |
| Redirecting output \Y: $procmux$288_CMP = $procmux$194_CMP |
| Removing $eq cell `$procmux$288_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$298_CMP0' is identical to cell `$procmux$153_CMP0'. |
| Redirecting output \Y: $procmux$298_CMP = $procmux$153_CMP |
| Removing $eq cell `$procmux$298_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$300_CMP0' is identical to cell `$procmux$155_CMP0'. |
| Redirecting output \Y: $procmux$300_CMP = $procmux$155_CMP |
| Removing $eq cell `$procmux$300_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$302_CMP0' is identical to cell `$procmux$157_CMP0'. |
| Redirecting output \Y: $procmux$302_CMP = $procmux$157_CMP |
| Removing $eq cell `$procmux$302_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$304_CMP0' is identical to cell `$procmux$159_CMP0'. |
| Redirecting output \Y: $procmux$304_CMP = $procmux$159_CMP |
| Removing $eq cell `$procmux$304_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$306_CMP0' is identical to cell `$procmux$161_CMP0'. |
| Redirecting output \Y: $procmux$306_CMP = $procmux$161_CMP |
| Removing $eq cell `$procmux$306_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$308_CMP0' is identical to cell `$procmux$163_CMP0'. |
| Redirecting output \Y: $procmux$308_CMP = $procmux$163_CMP |
| Removing $eq cell `$procmux$308_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$310_CMP0' is identical to cell `$procmux$165_CMP0'. |
| Redirecting output \Y: $procmux$310_CMP = $procmux$165_CMP |
| Removing $eq cell `$procmux$310_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$312_CMP0' is identical to cell `$procmux$167_CMP0'. |
| Redirecting output \Y: $procmux$312_CMP = $procmux$167_CMP |
| Removing $eq cell `$procmux$312_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$314_CMP0' is identical to cell `$procmux$169_CMP0'. |
| Redirecting output \Y: $procmux$314_CMP = $procmux$169_CMP |
| Removing $eq cell `$procmux$314_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$316_CMP0' is identical to cell `$procmux$171_CMP0'. |
| Redirecting output \Y: $procmux$316_CMP = $procmux$171_CMP |
| Removing $eq cell `$procmux$316_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$318_CMP0' is identical to cell `$procmux$173_CMP0'. |
| Redirecting output \Y: $procmux$318_CMP = $procmux$173_CMP |
| Removing $eq cell `$procmux$318_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$320_CMP0' is identical to cell `$procmux$175_CMP0'. |
| Redirecting output \Y: $procmux$320_CMP = $procmux$175_CMP |
| Removing $eq cell `$procmux$320_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$322_CMP0' is identical to cell `$procmux$177_CMP0'. |
| Redirecting output \Y: $procmux$322_CMP = $procmux$177_CMP |
| Removing $eq cell `$procmux$322_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$324_CMP0' is identical to cell `$procmux$179_CMP0'. |
| Redirecting output \Y: $procmux$324_CMP = $procmux$179_CMP |
| Removing $eq cell `$procmux$324_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$326_CMP0' is identical to cell `$procmux$181_CMP0'. |
| Redirecting output \Y: $procmux$326_CMP = $procmux$181_CMP |
| Removing $eq cell `$procmux$326_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$328_CMP0' is identical to cell `$procmux$183_CMP0'. |
| Redirecting output \Y: $procmux$328_CMP = $procmux$183_CMP |
| Removing $eq cell `$procmux$328_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$335_CMP0' is identical to cell `$procmux$194_CMP0'. |
| Redirecting output \Y: $procmux$335_CMP = $procmux$194_CMP |
| Removing $eq cell `$procmux$335_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$348_CMP0' is identical to cell `$procmux$159_CMP0'. |
| Redirecting output \Y: $procmux$348_CMP = $procmux$159_CMP |
| Removing $eq cell `$procmux$348_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$350_CMP0' is identical to cell `$procmux$161_CMP0'. |
| Redirecting output \Y: $procmux$350_CMP = $procmux$161_CMP |
| Removing $eq cell `$procmux$350_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$352_CMP0' is identical to cell `$procmux$163_CMP0'. |
| Redirecting output \Y: $procmux$352_CMP = $procmux$163_CMP |
| Removing $eq cell `$procmux$352_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$354_CMP0' is identical to cell `$procmux$165_CMP0'. |
| Redirecting output \Y: $procmux$354_CMP = $procmux$165_CMP |
| Removing $eq cell `$procmux$354_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$356_CMP0' is identical to cell `$procmux$167_CMP0'. |
| Redirecting output \Y: $procmux$356_CMP = $procmux$167_CMP |
| Removing $eq cell `$procmux$356_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$358_CMP0' is identical to cell `$procmux$169_CMP0'. |
| Redirecting output \Y: $procmux$358_CMP = $procmux$169_CMP |
| Removing $eq cell `$procmux$358_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$360_CMP0' is identical to cell `$procmux$171_CMP0'. |
| Redirecting output \Y: $procmux$360_CMP = $procmux$171_CMP |
| Removing $eq cell `$procmux$360_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$362_CMP0' is identical to cell `$procmux$173_CMP0'. |
| Redirecting output \Y: $procmux$362_CMP = $procmux$173_CMP |
| Removing $eq cell `$procmux$362_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$364_CMP0' is identical to cell `$procmux$175_CMP0'. |
| Redirecting output \Y: $procmux$364_CMP = $procmux$175_CMP |
| Removing $eq cell `$procmux$364_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$366_CMP0' is identical to cell `$procmux$177_CMP0'. |
| Redirecting output \Y: $procmux$366_CMP = $procmux$177_CMP |
| Removing $eq cell `$procmux$366_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$368_CMP0' is identical to cell `$procmux$179_CMP0'. |
| Redirecting output \Y: $procmux$368_CMP = $procmux$179_CMP |
| Removing $eq cell `$procmux$368_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$370_CMP0' is identical to cell `$procmux$181_CMP0'. |
| Redirecting output \Y: $procmux$370_CMP = $procmux$181_CMP |
| Removing $eq cell `$procmux$370_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$372_CMP0' is identical to cell `$procmux$183_CMP0'. |
| Redirecting output \Y: $procmux$372_CMP = $procmux$183_CMP |
| Removing $eq cell `$procmux$372_CMP0' from module `\i2c_master_bit_ctrl'. |
| Cell `$procmux$379_CMP0' is identical to cell `$procmux$194_CMP0'. |
| Redirecting output \Y: $procmux$379_CMP = $procmux$194_CMP |
| Removing $eq cell `$procmux$379_CMP0' from module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Cell `$logic_not$rtl/i2c_master_byte_ctrl.v:189$53' is identical to cell `$logic_not$rtl/i2c_master_byte_ctrl.v:178$51'. |
| Redirecting output \Y: $logic_not$rtl/i2c_master_byte_ctrl.v:189$53_Y = $logic_not$rtl/i2c_master_byte_ctrl.v:178$51_Y |
| Removing $logic_not cell `$logic_not$rtl/i2c_master_byte_ctrl.v:189$53' from module `\i2c_master_byte_ctrl'. |
| Cell `$logic_not$rtl/i2c_master_byte_ctrl.v:206$58' is identical to cell `$logic_not$rtl/i2c_master_byte_ctrl.v:178$51'. |
| Redirecting output \Y: $logic_not$rtl/i2c_master_byte_ctrl.v:206$58_Y = $logic_not$rtl/i2c_master_byte_ctrl.v:178$51_Y |
| Removing $logic_not cell `$logic_not$rtl/i2c_master_byte_ctrl.v:206$58' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$459_CMP0' is identical to cell `$procmux$415_CMP0'. |
| Redirecting output \Y: $procmux$459_CMP = $procmux$415_CMP |
| Removing $eq cell `$procmux$459_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$467_CMP0' is identical to cell `$procmux$421_CMP0'. |
| Redirecting output \Y: $procmux$467_CMP = $procmux$421_CMP |
| Removing $eq cell `$procmux$467_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$475_CMP0' is identical to cell `$procmux$427_CMP0'. |
| Redirecting output \Y: $procmux$475_CMP = $procmux$427_CMP |
| Removing $eq cell `$procmux$475_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$483_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$483_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$483_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$497_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$497_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$497_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$513_CMP0' is identical to cell `$procmux$415_CMP0'. |
| Redirecting output \Y: $procmux$513_CMP = $procmux$415_CMP |
| Removing $eq cell `$procmux$513_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$519_CMP0' is identical to cell `$procmux$421_CMP0'. |
| Redirecting output \Y: $procmux$519_CMP = $procmux$421_CMP |
| Removing $eq cell `$procmux$519_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$525_CMP0' is identical to cell `$procmux$427_CMP0'. |
| Redirecting output \Y: $procmux$525_CMP = $procmux$427_CMP |
| Removing $eq cell `$procmux$525_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$531_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$531_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$531_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$541_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$541_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$541_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$557_CMP0' is identical to cell `$procmux$415_CMP0'. |
| Redirecting output \Y: $procmux$557_CMP = $procmux$415_CMP |
| Removing $eq cell `$procmux$557_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$565_CMP0' is identical to cell `$procmux$421_CMP0'. |
| Redirecting output \Y: $procmux$565_CMP = $procmux$421_CMP |
| Removing $eq cell `$procmux$565_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$573_CMP0' is identical to cell `$procmux$427_CMP0'. |
| Redirecting output \Y: $procmux$573_CMP = $procmux$427_CMP |
| Removing $eq cell `$procmux$573_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$581_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$581_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$581_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$595_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$595_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$595_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$609_CMP0' is identical to cell `$procmux$415_CMP0'. |
| Redirecting output \Y: $procmux$609_CMP = $procmux$415_CMP |
| Removing $eq cell `$procmux$609_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$616_CMP0' is identical to cell `$procmux$421_CMP0'. |
| Redirecting output \Y: $procmux$616_CMP = $procmux$421_CMP |
| Removing $eq cell `$procmux$616_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$622_CMP0' is identical to cell `$procmux$427_CMP0'. |
| Redirecting output \Y: $procmux$622_CMP = $procmux$427_CMP |
| Removing $eq cell `$procmux$622_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$628_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$628_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$628_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$638_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$638_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$638_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$667_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$667_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$667_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$678_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$678_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$678_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$697_CMP0' is identical to cell `$procmux$421_CMP0'. |
| Redirecting output \Y: $procmux$697_CMP = $procmux$421_CMP |
| Removing $eq cell `$procmux$697_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$705_CMP0' is identical to cell `$procmux$427_CMP0'. |
| Redirecting output \Y: $procmux$705_CMP = $procmux$427_CMP |
| Removing $eq cell `$procmux$705_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$711_CMP0' is identical to cell `$procmux$433_CMP0'. |
| Redirecting output \Y: $procmux$711_CMP = $procmux$433_CMP |
| Removing $eq cell `$procmux$711_CMP0' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$721_CMP0' is identical to cell `$procmux$443_CMP0'. |
| Redirecting output \Y: $procmux$721_CMP = $procmux$443_CMP |
| Removing $eq cell `$procmux$721_CMP0' from module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Cell `$and$rtl/i2c_master_top.v:164$64' is identical to cell `$and$rtl/i2c_master_top.v:160$61'. |
| Redirecting output \Y: $and$rtl/i2c_master_top.v:164$64_Y = $and$rtl/i2c_master_top.v:160$61_Y |
| Removing $and cell `$and$rtl/i2c_master_top.v:164$64' from module `\i2c_master_top'. |
| Cell `$logic_not$rtl/i2c_master_top.v:266$76' is identical to cell `$logic_not$rtl/i2c_master_top.v:183$69'. |
| Redirecting output \Y: $logic_not$rtl/i2c_master_top.v:266$76_Y = $logic_not$rtl/i2c_master_top.v:183$69_Y |
| Removing $logic_not cell `$logic_not$rtl/i2c_master_top.v:266$76' from module `\i2c_master_top'. |
| Cell `$logic_not$rtl/i2c_master_top.v:290$86' is identical to cell `$logic_not$rtl/i2c_master_top.v:183$69'. |
| Redirecting output \Y: $logic_not$rtl/i2c_master_top.v:290$86_Y = $logic_not$rtl/i2c_master_top.v:183$69_Y |
| Removing $logic_not cell `$logic_not$rtl/i2c_master_top.v:290$86' from module `\i2c_master_top'. |
| Cell `$or$rtl/i2c_master_top.v:285$81' is identical to cell `$or$rtl/i2c_master_top.v:218$74'. |
| Redirecting output \Y: $or$rtl/i2c_master_top.v:285$81_Y = $or$rtl/i2c_master_top.v:218$74_Y |
| Removing $or cell `$or$rtl/i2c_master_top.v:285$81' from module `\i2c_master_top'. |
| Cell `$procmux$732_CMP0' is identical to cell `$eq$rtl/i2c_master_top.v:213$72'. |
| Redirecting output \Y: $procmux$732_CMP = $eq$rtl/i2c_master_top.v:213$72_Y |
| Removing $eq cell `$procmux$732_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$745_CMP0' is identical to cell `$procmux$736_CMP0'. |
| Redirecting output \Y: $procmux$745_CMP = $procmux$736_CMP |
| Removing $eq cell `$procmux$745_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$747_CMP0' is identical to cell `$procmux$738_CMP0'. |
| Redirecting output \Y: $procmux$747_CMP = $procmux$738_CMP |
| Removing $eq cell `$procmux$747_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$749_CMP0' is identical to cell `$procmux$740_CMP0'. |
| Redirecting output \Y: $procmux$749_CMP = $procmux$740_CMP |
| Removing $eq cell `$procmux$749_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$762_CMP0' is identical to cell `$procmux$740_CMP0'. |
| Redirecting output \Y: $procmux$762_CMP = $procmux$740_CMP |
| Removing $eq cell `$procmux$762_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$774_CMP0' is identical to cell `$procmux$738_CMP0'. |
| Redirecting output \Y: $procmux$774_CMP = $procmux$738_CMP |
| Removing $eq cell `$procmux$774_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$776_CMP0' is identical to cell `$procmux$740_CMP0'. |
| Redirecting output \Y: $procmux$776_CMP = $procmux$740_CMP |
| Removing $eq cell `$procmux$776_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$786_CMP0' is identical to cell `$procmux$734_CMP0'. |
| Redirecting output \Y: $procmux$786_CMP = $procmux$734_CMP |
| Removing $eq cell `$procmux$786_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$788_CMP0' is identical to cell `$procmux$736_CMP0'. |
| Redirecting output \Y: $procmux$788_CMP = $procmux$736_CMP |
| Removing $eq cell `$procmux$788_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$790_CMP0' is identical to cell `$procmux$738_CMP0'. |
| Redirecting output \Y: $procmux$790_CMP = $procmux$738_CMP |
| Removing $eq cell `$procmux$790_CMP0' from module `\i2c_master_top'. |
| Cell `$procmux$792_CMP0' is identical to cell `$procmux$740_CMP0'. |
| Redirecting output \Y: $procmux$792_CMP = $procmux$740_CMP |
| Removing $eq cell `$procmux$792_CMP0' from module `\i2c_master_top'. |
| Removed a total of 115 cells. |
| |
| 7.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 7.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| New ctrl vector for $pmux cell $procmux$152: { $procmux$194_CMP $procmux$183_CMP $procmux$181_CMP $procmux$179_CMP $procmux$177_CMP $procmux$173_CMP $procmux$171_CMP $procmux$169_CMP $procmux$165_CMP $procmux$163_CMP $procmux$161_CMP $procmux$157_CMP $procmux$155_CMP $procmux$153_CMP } |
| New ctrl vector for $pmux cell $procmux$203: $auto$opt_reduce.cc:123:opt_mux$906 |
| New ctrl vector for $pmux cell $procmux$250: { $auto$opt_reduce.cc:123:opt_mux$910 $auto$opt_reduce.cc:123:opt_mux$908 } |
| New ctrl vector for $pmux cell $procmux$297: $auto$opt_reduce.cc:123:opt_mux$912 |
| New ctrl vector for $pmux cell $procmux$347: { $procmux$194_CMP $auto$opt_reduce.cc:123:opt_mux$916 $auto$opt_reduce.cc:123:opt_mux$914 } |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| New ctrl vector for $pmux cell $procmux$414: $procmux$415_CMP |
| New ctrl vector for $pmux cell $procmux$512: { $auto$opt_reduce.cc:123:opt_mux$918 $procmux$415_CMP } |
| New ctrl vector for $pmux cell $procmux$608: { $procmux$421_CMP $procmux$415_CMP } |
| New ctrl vector for $pmux cell $procmux$696: { $procmux$427_CMP $procmux$421_CMP } |
| Optimizing cells in module \i2c_master_top. |
| New ctrl vector for $pmux cell $procmux$744: $procmux$736_CMP |
| New ctrl vector for $pmux cell $procmux$773: $procmux$738_CMP |
| New ctrl vector for $pmux cell $procmux$785: $procmux$734_CMP |
| Performed a total of 12 changes. |
| |
| 7.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$664' is identical to cell `$procmux$503'. |
| Redirecting output \Y: $procmux$664_Y = $procmux$503_Y |
| Removing $mux cell `$procmux$664' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$694' is identical to cell `$procmux$503'. |
| Redirecting output \Y: $procmux$694_Y = $procmux$503_Y |
| Removing $mux cell `$procmux$694' from module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 2 cells. |
| |
| 7.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 7.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| removing unused `$logic_not' cell `$logic_not$rtl/i2c_master_bit_ctrl.v:283$23'. |
| removing unused `$not' cell `$not$rtl/i2c_master_bit_ctrl.v:201$5'. |
| removed 120 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| removing unused `$logic_not' cell `$logic_not$rtl/i2c_master_byte_ctrl.v:178$51'. |
| removed 92 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_top.. |
| removing unused `$not' cell `$not$rtl/i2c_master_top.v:207$71'. |
| removing unused `$logic_not' cell `$logic_not$rtl/i2c_master_top.v:183$69'. |
| removed 60 unused temporary wires. |
| |
| 7.9. Executing OPT_CONST pass (perform const folding). |
| |
| 7.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 7.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 7.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| Optimizing cells in module \i2c_master_top. |
| Performed a total of 0 changes. |
| |
| 7.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 7.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 7.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| Finding unused cells or wires in module \i2c_master_top.. |
| |
| 7.16. Executing OPT_CONST pass (perform const folding). |
| |
| 7.17. Optimizing in-memory representation of design. |
| |
| 7.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 8. Executing MEMORY pass. |
| |
| 8.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| |
| 8.2. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 8.3. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| |
| 9. Executing OPT pass (performing simple optimizations). |
| |
| 9.1. Optimizing in-memory representation of design. |
| |
| 9.2. Executing OPT_CONST pass (perform const folding). |
| |
| 9.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 9.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 9.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| Optimizing cells in module \i2c_master_top. |
| Performed a total of 0 changes. |
| |
| 9.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 9.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 9.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| Finding unused cells or wires in module \i2c_master_top.. |
| |
| 9.9. Executing OPT_CONST pass (perform const folding). |
| |
| 9.10. Optimizing in-memory representation of design. |
| |
| 9.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 10. Executing TECHMAP pass (map to technology primitives). |
| |
| 10.1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog <stdcells.v> |
| Parsing Verilog input from `<stdcells.v>' to AST representation. |
| Generating RTLIL representation for module `\$not'. |
| Generating RTLIL representation for module `\$pos'. |
| Generating RTLIL representation for module `\$neg'. |
| Generating RTLIL representation for module `\$and'. |
| Generating RTLIL representation for module `\$or'. |
| Generating RTLIL representation for module `\$xor'. |
| Generating RTLIL representation for module `\$xnor'. |
| Generating RTLIL representation for module `\$reduce_and'. |
| Generating RTLIL representation for module `\$reduce_or'. |
| Generating RTLIL representation for module `\$reduce_xor'. |
| Generating RTLIL representation for module `\$reduce_xnor'. |
| Generating RTLIL representation for module `\$reduce_bool'. |
| Generating RTLIL representation for module `\$shift'. |
| Generating RTLIL representation for module `\$shl'. |
| Generating RTLIL representation for module `\$shr'. |
| Generating RTLIL representation for module `\$sshl'. |
| Generating RTLIL representation for module `\$sshr'. |
| Generating RTLIL representation for module `\$fulladd'. |
| Generating RTLIL representation for module `\$alu'. |
| Generating RTLIL representation for module `\$lt'. |
| Generating RTLIL representation for module `\$le'. |
| Generating RTLIL representation for module `\$eq'. |
| Generating RTLIL representation for module `\$ne'. |
| Generating RTLIL representation for module `\$ge'. |
| Generating RTLIL representation for module `\$gt'. |
| Generating RTLIL representation for module `\$add'. |
| Generating RTLIL representation for module `\$sub'. |
| Generating RTLIL representation for module `\$logic_not'. |
| Generating RTLIL representation for module `\$logic_and'. |
| Generating RTLIL representation for module `\$logic_or'. |
| Generating RTLIL representation for module `\$mux'. |
| Generating RTLIL representation for module `\$pmux'. |
| Generating RTLIL representation for module `\$safe_pmux'. |
| Generating RTLIL representation for module `\$dff'. |
| Generating RTLIL representation for module `\$adff'. |
| Successfully finished Verilog frontend. |
| |
| 10.2. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.3. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$17' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$18' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$20' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$21' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:288$26' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$33' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$34' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$36' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$38' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:314$42' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.4. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 14 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=14\Y_WIDTH=1'. |
| |
| 10.5. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$907' using `$paramod$reduce_or\A_WIDTH=14\Y_WIDTH=1'. |
| |
| 10.6. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 10 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=10\Y_WIDTH=1'. |
| |
| 10.7. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$909' using `$paramod$reduce_or\A_WIDTH=10\Y_WIDTH=1'. |
| |
| 10.8. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.9. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$911' using `$paramod$reduce_or\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$913' using `$paramod$reduce_or\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.10. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 7 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=7\Y_WIDTH=1'. |
| |
| 10.11. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$915' using `$paramod$reduce_or\A_WIDTH=7\Y_WIDTH=1'. |
| |
| 10.12. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 6 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=6\Y_WIDTH=1'. |
| |
| 10.13. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$auto$opt_reduce.cc:127:opt_mux$917' using `$paramod$reduce_or\A_WIDTH=6\Y_WIDTH=1'. |
| |
| 10.14. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.15. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$eq$rtl/i2c_master_bit_ctrl.v:301$29' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.16. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.17. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$logic_and$rtl/i2c_master_bit_ctrl.v:196$3' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.18. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.19. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$logic_not$rtl/i2c_master_bit_ctrl.v:196$2' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.20. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.21. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$logic_or$rtl/i2c_master_bit_ctrl.v:211$9' using `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.22. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.23. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:211$7' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:211$8' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:212$10' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:277$16' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:278$19' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:288$25' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:309$37' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$not$rtl/i2c_master_bit_ctrl.v:314$41' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.24. Executing AST frontend in derive mode using pre-parsed AST for module `$or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.25. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:288$24' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:309$39' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:348$45' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.26. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.27. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procdff$868' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.28. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 1'1 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| |
| 10.29. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procdff$869' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| |
| 10.30. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 16 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 16'0000000000000000 |
| Generating RTLIL representation for module `$paramod$9174d9be0ab84888e2ccae53ceee880cc1370605$adff'. |
| |
| 10.31. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procdff$870' using `$paramod$9174d9be0ab84888e2ccae53ceee880cc1370605$adff'. |
| Mapping `i2c_master_bit_ctrl.$procdff$871' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| Mapping `i2c_master_bit_ctrl.$procdff$872' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| Mapping `i2c_master_bit_ctrl.$procdff$873' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| Mapping `i2c_master_bit_ctrl.$procdff$874' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| |
| 10.32. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 1'0 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 10.33. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procdff$875' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$876' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$877' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$878' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$879' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$880' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.34. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 17 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 17'00000000000000000 |
| Generating RTLIL representation for module `$paramod$352fec55ecf061ee3cf99484644be64518759d3e$adff'. |
| |
| 10.35. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procdff$881' using `$paramod$352fec55ecf061ee3cf99484644be64518759d3e$adff'. |
| Mapping `i2c_master_bit_ctrl.$procdff$882' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$883' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| Mapping `i2c_master_bit_ctrl.$procdff$884' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_bit_ctrl.$procdff$885' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'1'. |
| |
| 10.36. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=16'. |
| |
| 10.37. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$100' using `$paramod$mux\WIDTH=16'. |
| Mapping `i2c_master_bit_ctrl.$procmux$102' using `$paramod$mux\WIDTH=16'. |
| Mapping `i2c_master_bit_ctrl.$procmux$105' using `$paramod$mux\WIDTH=16'. |
| |
| 10.38. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=1'. |
| |
| 10.39. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$109' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$113' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$117' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$121' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$125' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$129' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$133' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$137' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$140' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$144' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$148' using `$paramod$mux\WIDTH=1'. |
| |
| 10.40. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 17 |
| Parameter \S_WIDTH = 14 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=17\S_WIDTH=14'. |
| |
| 10.41. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$152' using `$paramod$pmux\WIDTH=17\S_WIDTH=14'. |
| |
| 10.42. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 17 |
| Parameter \B_WIDTH = 17 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.43. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$153_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$155_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$157_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$159_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$161_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$163_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$165_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$167_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$169_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$171_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$173_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$175_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$177_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$179_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$181_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$183_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.44. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 17 |
| Parameter \S_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=17\S_WIDTH=4'. |
| |
| 10.45. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$185' using `$paramod$pmux\WIDTH=17\S_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$186_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$188_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$192_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$194_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.46. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 17 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=17'. |
| |
| 10.47. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$195' using `$paramod$mux\WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$198' using `$paramod$mux\WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$203' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$242' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$245' using `$paramod$mux\WIDTH=1'. |
| |
| 10.48. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 1 |
| Parameter \S_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| |
| 10.49. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$250' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| Mapping `i2c_master_bit_ctrl.$procmux$289' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$292' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$297' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$336' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$339' using `$paramod$mux\WIDTH=1'. |
| |
| 10.50. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 1 |
| Parameter \S_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=3'. |
| |
| 10.51. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$347' using `$paramod$pmux\WIDTH=1\S_WIDTH=3'. |
| Mapping `i2c_master_bit_ctrl.$procmux$380' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$383' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$90' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$92' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$procmux$95' using `$paramod$mux\WIDTH=1'. |
| |
| 10.52. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 16 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=16\Y_WIDTH=1'. |
| |
| 10.53. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$reduce_or$rtl/i2c_master_bit_ctrl.v:211$6' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=16\Y_WIDTH=1'. |
| |
| 10.54. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 17 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.55. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.56. Executing AST frontend in derive mode using pre-parsed AST for module `$sub'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 16 |
| Parameter \B_WIDTH = 16 |
| Parameter \Y_WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16'. |
| |
| 10.57. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11' using `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16'. |
| Mapping `i2c_master_byte_ctrl.$and$rtl/i2c_master_byte_ctrl.v:171$49' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.58. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.59. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$auto$opt_reduce.cc:127:opt_mux$919' using `$paramod$reduce_or\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$not$rtl/i2c_master_byte_ctrl.v:171$48' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$not$rtl/i2c_master_byte_ctrl.v:198$56' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$46' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$47' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:216$59' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.60. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 8'00000000 |
| Generating RTLIL representation for module `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| |
| 10.61. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procdff$886' using `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| |
| 10.62. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 3 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 3'000 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=3\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=3'000'. |
| |
| 10.63. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procdff$887' using `$paramod$adff\WIDTH=3\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=3'000'. |
| Mapping `i2c_master_byte_ctrl.$procdff$888' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 10.64. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 5 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 5'00000 |
| Generating RTLIL representation for module `$paramod$25557f4fe17a57b84f82bad569255c6681aaf1e5$adff'. |
| |
| 10.65. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procdff$889' using `$paramod$25557f4fe17a57b84f82bad569255c6681aaf1e5$adff'. |
| Mapping `i2c_master_byte_ctrl.$procdff$890' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 10.66. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 4 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 4'0000 |
| Generating RTLIL representation for module `$paramod$0cf2c4a7871717ef6d7619eb711d526c80df9027$adff'. |
| |
| 10.67. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procdff$891' using `$paramod$0cf2c4a7871717ef6d7619eb711d526c80df9027$adff'. |
| Mapping `i2c_master_byte_ctrl.$procdff$892' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_byte_ctrl.$procdff$893' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_byte_ctrl.$procdff$894' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 10.68. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=8'. |
| |
| 10.69. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$387' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_byte_ctrl.$procmux$390' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_byte_ctrl.$procmux$393' using `$paramod$mux\WIDTH=8'. |
| |
| 10.70. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=3'. |
| |
| 10.71. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$397' using `$paramod$mux\WIDTH=3'. |
| Mapping `i2c_master_byte_ctrl.$procmux$400' using `$paramod$mux\WIDTH=3'. |
| Mapping `i2c_master_byte_ctrl.$procmux$403' using `$paramod$mux\WIDTH=3'. |
| Mapping `i2c_master_byte_ctrl.$procmux$412' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$414' using `$paramod$mux\WIDTH=1'. |
| |
| 10.72. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 5 |
| Parameter \B_WIDTH = 5 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| |
| 10.73. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$415_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$421_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$427_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$433_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$443_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$445' using `$paramod$mux\WIDTH=1'. |
| |
| 10.74. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=5'. |
| |
| 10.75. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$449' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$454' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$456' using `$paramod$mux\WIDTH=5'. |
| |
| 10.76. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 5 |
| Parameter \S_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=5\S_WIDTH=5'. |
| |
| 10.77. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$458' using `$paramod$pmux\WIDTH=5\S_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$462' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$464' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$470' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$472' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$478' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$480' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$486' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$489' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$492' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$494' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$499' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$503' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$508' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$510' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$512' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| Mapping `i2c_master_byte_ctrl.$procmux$543' using `$paramod$mux\WIDTH=1'. |
| |
| 10.78. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=4'. |
| |
| 10.79. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$547' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$552' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$554' using `$paramod$mux\WIDTH=4'. |
| |
| 10.80. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 4 |
| Parameter \S_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=4\S_WIDTH=5'. |
| |
| 10.81. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$556' using `$paramod$pmux\WIDTH=4\S_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$560' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$562' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$568' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$570' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$576' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$578' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$584' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$587' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$590' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$592' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$597' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$procmux$606' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$608' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| Mapping `i2c_master_byte_ctrl.$procmux$613' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$640' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$666' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| Mapping `i2c_master_byte_ctrl.$procmux$675' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$680' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$696' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'. |
| Mapping `i2c_master_byte_ctrl.$procmux$700' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$702' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$procmux$723' using `$paramod$mux\WIDTH=1'. |
| |
| 10.82. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| |
| 10.83. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$reduce_or$rtl/i2c_master_byte_ctrl.v:198$55' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| |
| 10.84. Executing AST frontend in derive mode using pre-parsed AST for module `$sub'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.85. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54' using `$paramod$sub\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$61' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$62' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:164$66' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:213$73' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:282$78' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:285$84' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.86. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| |
| 10.87. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$eq$rtl/i2c_master_top.v:213$72' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$logic_and$rtl/i2c_master_top.v:295$87' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$not$rtl/i2c_master_top.v:164$65' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$not$rtl/i2c_master_top.v:282$77' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$not$rtl/i2c_master_top.v:285$83' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:218$74' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:282$79' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:284$80' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:285$82' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procdff$895' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.88. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 10.89. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$procdff$896' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `i2c_master_top.$procdff$897' using `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| |
| 10.90. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 16 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 16'1111111111111111 |
| Generating RTLIL representation for module `$paramod$af18f83badd4c8e4178550478c969b4e06b22d66$adff'. |
| |
| 10.91. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$procdff$898' using `$paramod$af18f83badd4c8e4178550478c969b4e06b22d66$adff'. |
| Mapping `i2c_master_top.$procdff$899' using `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| Mapping `i2c_master_top.$procdff$900' using `$paramod$085b02837c2a3c54dbc4d697f27653fe1c887dc0$adff'. |
| Mapping `i2c_master_top.$procdff$901' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_top.$procdff$902' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_top.$procdff$903' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_top.$procdff$904' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| Mapping `i2c_master_top.$procdff$905' using `$paramod$adff\WIDTH=1\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=1'0'. |
| |
| 10.92. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 8 |
| Parameter \S_WIDTH = 7 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=8\S_WIDTH=7'. |
| |
| 10.93. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$procmux$727' using `$paramod$pmux\WIDTH=8\S_WIDTH=7'. |
| Mapping `i2c_master_top.$procmux$728_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$730_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$734_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$736_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$738_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$740_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$744' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$750' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$753' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$761' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$763' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$766' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$773' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$777' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$780' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$785' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$793' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$procmux$796' using `$paramod$mux\WIDTH=8'. |
| |
| 10.94. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=2'. |
| |
| 10.95. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$procmux$803' using `$paramod$mux\WIDTH=2'. |
| Mapping `i2c_master_top.$procmux$805' using `$paramod$mux\WIDTH=2'. |
| Mapping `i2c_master_top.$procmux$808' using `$paramod$mux\WIDTH=2'. |
| Mapping `i2c_master_top.$procmux$815' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$817' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$820' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$824' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_top.$procmux$828' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_top.$procmux$830' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_top.$procmux$833' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_top.$procmux$840' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$842' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$845' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$849' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$853' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$857' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$861' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$865' using `$paramod$mux\WIDTH=1'. |
| |
| 10.96. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.97. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$xor$rtl/i2c_master_top.v:157$60' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.98. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.99. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$17.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$17.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$18.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:277$18.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$20.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$20.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$21.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:278$21.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:288$26.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:288$26.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$33.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$33.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$34.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$34.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$36.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$36.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$38.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:309$38.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:314$42.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$and$rtl/i2c_master_bit_ctrl.v:314$42.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.100. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.101. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$eq$rtl/i2c_master_bit_ctrl.v:301$29.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$eq$rtl/i2c_master_bit_ctrl.v:301$29.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.102. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_bool'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| |
| 10.103. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$logic_and$rtl/i2c_master_bit_ctrl.v:196$3.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$logic_and$rtl/i2c_master_bit_ctrl.v:196$3.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$logic_not$rtl/i2c_master_bit_ctrl.v:196$2.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$logic_or$rtl/i2c_master_bit_ctrl.v:211$9.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$logic_or$rtl/i2c_master_bit_ctrl.v:211$9.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:288$24.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:288$24.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:309$39.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:309$39.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:348$45.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$or$rtl/i2c_master_bit_ctrl.v:348$45.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.104. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 17 |
| Parameter \Y_WIDTH = 17 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.105. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$procmux$153_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$153_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$155_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$155_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$157_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$157_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$159_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$159_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$161_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$161_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$163_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$163_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$165_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$165_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$167_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$167_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$169_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$169_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$171_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$171_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$173_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$173_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$175_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$175_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$177_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$177_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$179_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$179_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$181_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$181_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$183_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$183_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$186_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$186_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$188_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$188_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$192_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$192_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$procmux$194_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$procmux$194_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.106. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 16 |
| Parameter \Y_WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=16\Y_WIDTH=16'. |
| |
| 10.107. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=16\Y_WIDTH=16'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=16\Y_WIDTH=16'. |
| |
| 10.108. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=16'. |
| |
| 10.109. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu' using `$paramod$alu\WIDTH=16'. |
| Mapping `i2c_master_bit_ctrl.$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$not$<stdcells.v>:808$949' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.110. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.111. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$reduce_or$<stdcells.v>:808$948' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.112. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.113. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.114. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 17 |
| Parameter \B_WIDTH = 17 |
| Parameter \Y_WIDTH = 17 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.115. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$952' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$953' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$954' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$955' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$956' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$957' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$958' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$959' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$960' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$961' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$962' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$963' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$964' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$965' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.116. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 14 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| |
| 10.117. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=14\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$ternary$<stdcells.v>:1214$951' using `$paramod$mux\WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$153_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| |
| 10.118. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 17 |
| Parameter \B_WIDTH = 17 |
| Parameter \Y_WIDTH = 17 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.119. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$155_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$157_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$159_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$161_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$163_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$165_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$167_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$169_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$171_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$173_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$175_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$177_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$179_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$179_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$181_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$181_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$183_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$183_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$988' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$989' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$990' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$991' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$reduce_or$<stdcells.v>:1214$986' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$ternary$<stdcells.v>:1214$987' using `$paramod$mux\WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$186_CMP0.$not$<stdcells.v>:808$949' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$948' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$188_CMP0.$not$<stdcells.v>:808$949' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$948' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$192_CMP0.$not$<stdcells.v>:808$949' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$192_CMP0.$reduce_or$<stdcells.v>:808$948' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$194_CMP0.$not$<stdcells.v>:808$985' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=17\B_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1011' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1012' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.120. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.121. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$reduce_or$<stdcells.v>:1210$1013' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$reduce_or$<stdcells.v>:1214$1009' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$ternary$<stdcells.v>:1214$1010' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1016' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1017' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1018' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$reduce_or$<stdcells.v>:1210$1019' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$reduce_or$<stdcells.v>:1214$1014' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$ternary$<stdcells.v>:1214$1015' using `$paramod$mux\WIDTH=1'. |
| |
| 10.122. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 16 |
| Parameter \Y_WIDTH = 16 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=16\Y_WIDTH=16'. |
| |
| 10.123. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020' using `$paramod$not\A_SIGNED=0\A_WIDTH=16\Y_WIDTH=16'. |
| Mapping `i2c_master_byte_ctrl.$and$rtl/i2c_master_byte_ctrl.v:171$49.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$and$rtl/i2c_master_byte_ctrl.v:171$49.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$46.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$46.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$47.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:171$47.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:216$59.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$or$rtl/i2c_master_byte_ctrl.v:216$59.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.124. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 5 |
| Parameter \Y_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.125. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$procmux$415_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$415_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$421_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$421_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$427_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$427_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$433_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$433_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$443_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$procmux$443_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.126. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.127. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.128. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=3'. |
| |
| 10.129. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu' using `$paramod$alu\WIDTH=3'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$415_CMP0.$not$<stdcells.v>:808$1023' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.130. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 5 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| |
| 10.131. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| |
| 10.132. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 5 |
| Parameter \B_WIDTH = 5 |
| Parameter \Y_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.133. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$421_CMP0.$not$<stdcells.v>:808$1023' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$421_CMP0.$reduce_or$<stdcells.v>:808$1022' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$427_CMP0.$not$<stdcells.v>:808$1023' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$427_CMP0.$reduce_or$<stdcells.v>:808$1022' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$433_CMP0.$not$<stdcells.v>:808$1023' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$433_CMP0.$reduce_or$<stdcells.v>:808$1022' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$443_CMP0.$not$<stdcells.v>:808$1023' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.134. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 5 |
| Parameter \B_WIDTH = 5 |
| Parameter \Y_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.135. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1026' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1027' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1028' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1029' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1030' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1210$1031' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1210$1032' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1210$1033' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1210$1034' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1210$1035' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$ternary$<stdcells.v>:1214$1025' using `$paramod$mux\WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1011' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1012' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$reduce_or$<stdcells.v>:1210$1013' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$reduce_or$<stdcells.v>:1214$1009' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$ternary$<stdcells.v>:1214$1010' using `$paramod$mux\WIDTH=1'. |
| |
| 10.136. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.137. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1038' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1039' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1040' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1041' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1042' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$reduce_or$<stdcells.v>:1210$1043' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$reduce_or$<stdcells.v>:1210$1044' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$reduce_or$<stdcells.v>:1210$1045' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$reduce_or$<stdcells.v>:1210$1046' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$ternary$<stdcells.v>:1214$1037' using `$paramod$mux\WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1011' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1012' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$reduce_or$<stdcells.v>:1210$1013' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$reduce_or$<stdcells.v>:1214$1009' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$ternary$<stdcells.v>:1214$1010' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1011' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1012' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$reduce_or$<stdcells.v>:1210$1013' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$reduce_or$<stdcells.v>:1214$1009' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$ternary$<stdcells.v>:1214$1010' using `$paramod$mux\WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1011' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1012' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$reduce_or$<stdcells.v>:1210$1013' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$reduce_or$<stdcells.v>:1214$1009' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$ternary$<stdcells.v>:1214$1010' using `$paramod$mux\WIDTH=1'. |
| |
| 10.138. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.139. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047' using `$paramod$not\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$61.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$61.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$62.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:160$62.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:164$66.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:164$66.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:213$73.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:213$73.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:282$78.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:282$78.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:285$84.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$and$rtl/i2c_master_top.v:285$84.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$eq$rtl/i2c_master_top.v:213$72.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$eq$rtl/i2c_master_top.v:213$72.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$logic_and$rtl/i2c_master_top.v:295$87.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_top.$logic_and$rtl/i2c_master_top.v:295$87.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:218$74.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:218$74.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:282$79.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:282$79.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:284$80.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:284$80.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:285$82.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$or$rtl/i2c_master_top.v:285$82.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$procmux$728_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$728_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$730_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$730_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$734_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$734_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$736_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$736_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$738_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$738_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$740_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$procmux$740_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$eq$rtl/i2c_master_top.v:213$72.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$eq$rtl/i2c_master_top.v:213$72.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| |
| 10.140. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \B_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.141. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.142. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \B_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| |
| 10.143. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1053' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1054' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1055' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1056' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1057' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1058' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1059' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. |
| |
| 10.144. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 7 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| |
| 10.145. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1060' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1061' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1062' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1063' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1064' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1065' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1066' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1067' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$reduce_or$<stdcells.v>:1214$1051' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$ternary$<stdcells.v>:1214$1052' using `$paramod$mux\WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$728_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$728_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$730_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$730_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$734_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$734_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$736_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$736_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$738_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$738_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$740_CMP0.$not$<stdcells.v>:808$1050' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$740_CMP0.$reduce_or$<stdcells.v>:808$1049' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$xor$rtl/i2c_master_top.v:157$60.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_top.$xor$rtl/i2c_master_top.v:157$60.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[10].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[11].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[12].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[13].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[14].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[15].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[1].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[2].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[3].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[4].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[5].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[6].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[7].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[8].adder' using `$fulladd'. |
| Mapping `i2c_master_bit_ctrl.$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[9].adder' using `$fulladd'. |
| |
| 10.146. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.147. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.148. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 17 |
| Parameter \Y_WIDTH = 17 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| |
| 10.149. Continuing TECHMAP pass. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$952.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$952.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$953.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$953.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$954.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$954.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$955.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$955.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$956.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$956.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$957.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$957.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$958.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$958.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$959.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$959.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$960.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$960.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$961.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$961.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$962.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$962.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$963.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$963.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$964.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$964.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$965.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$152.$and$<stdcells.v>:1203$965.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$988.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$988.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$989.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$989.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$990.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$990.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$991.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$185.$and$<stdcells.v>:1203$991.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=17\Y_WIDTH=17'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1011.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1011.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1012.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$250.$and$<stdcells.v>:1203$1012.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1016.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1016.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1017.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1017.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1018.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_bit_ctrl.$techmap$procmux$347.$and$<stdcells.v>:1203$1018.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder' using `$fulladd'. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[1].adder' using `$fulladd'. |
| Mapping `i2c_master_byte_ctrl.$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[2].adder' using `$fulladd'. |
| |
| 10.150. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 5 |
| Parameter \Y_WIDTH = 5 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| |
| 10.151. Continuing TECHMAP pass. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1026.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1026.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1027.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1027.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1028.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1028.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1029.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1029.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1030.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$458.$and$<stdcells.v>:1203$1030.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1011.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1011.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1012.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$512.$and$<stdcells.v>:1203$1012.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1038.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1038.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1039.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1039.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1040.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1040.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1041.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1041.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1042.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$556.$and$<stdcells.v>:1203$1042.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1011.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1011.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1012.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$608.$and$<stdcells.v>:1203$1012.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1011.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1011.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1012.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$666.$and$<stdcells.v>:1203$1012.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1011.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1011.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1012.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `i2c_master_byte_ctrl.$techmap$procmux$696.$and$<stdcells.v>:1203$1012.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.152. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.153. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| |
| 10.154. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 8 |
| Parameter \Y_WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| |
| 10.155. Continuing TECHMAP pass. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1053.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1053.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1054.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1054.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1055.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1055.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1056.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1056.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1057.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1057.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1058.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1058.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1059.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$727.$and$<stdcells.v>:1203$1059.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=8\Y_WIDTH=8'. |
| Mapping `i2c_master_top.$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| Mapping `i2c_master_top.$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'. |
| No more expansions possible. |
| |
| 11. Executing OPT pass (performing simple optimizations). |
| |
| 11.1. Optimizing in-memory representation of design. |
| |
| 11.2. Executing OPT_CONST pass (perform const folding). |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.gate3' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.t3 = $sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.t2'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.Y [0] = \cmd [0]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.Y [2] = \cmd [2]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$xor$<stdcells.v>:808$947.Y [3] = \cmd [3]'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[16].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [16] = $techmap$procmux$153_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$952.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$952.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[15].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [15] = $techmap$procmux$155_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$953.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$953.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[14].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [14] = $techmap$procmux$157_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$954.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$954.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[12].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [12] = $techmap$procmux$161_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$955.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$955.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[11].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [11] = $techmap$procmux$163_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$956.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$956.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[10].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [10] = $techmap$procmux$165_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$957.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$957.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[8].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [8] = $techmap$procmux$169_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$958.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$958.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[7].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [7] = $techmap$procmux$171_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$959.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$959.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[6].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [6] = $techmap$procmux$173_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$960.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$960.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[4].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [4] = $techmap$procmux$177_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$961.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$961.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[3].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [3] = $techmap$procmux$179_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$962.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$962.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[2].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [2] = $techmap$procmux$181_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$963.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$963.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[1].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [1] = $techmap$procmux$183_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$964.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$964.Y [9] = 1'0'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$153_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$155_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$157_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$159_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$161_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$163_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$165_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$167_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$169_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$171_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$173_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$175_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$177_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$179_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$181_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$183_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$988.V[9].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$988.Y [9] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[13].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [13] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$989.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$989.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[5].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [5] = $techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$990.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$990.Y [9] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[0].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [0] = $techmap$procmux$192_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [13] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [5] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$185.$and$<stdcells.v>:1203$991.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$and$<stdcells.v>:1203$991.Y [9] = 1'0'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.Y [0] = \cmd [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.Y [1] = \cmd [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$186_CMP0.$xor$<stdcells.v>:808$947.Y [2] = \cmd [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.Y [0] = \cmd [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.Y [1] = \cmd [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$188_CMP0.$xor$<stdcells.v>:808$947.Y [3] = \cmd [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.Y [1] = \cmd [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.Y [2] = \cmd [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$192_CMP0.$xor$<stdcells.v>:808$947.Y [3] = \cmd [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[0].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [0] = $procdff$881.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [10] = $procdff$881.Q [10]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [11] = $procdff$881.Q [11]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [12] = $procdff$881.Q [12]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [13] = $procdff$881.Q [13]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[14].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [14] = $procdff$881.Q [14]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[15].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [15] = $procdff$881.Q [15]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[16].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [16] = $procdff$881.Q [16]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [1] = $procdff$881.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [2] = $procdff$881.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [3] = $procdff$881.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [4] = $procdff$881.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [5] = $procdff$881.Q [5]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [6] = $procdff$881.Q [6]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [7] = $procdff$881.Q [7]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [8] = $procdff$881.Q [8]'. |
| Replacing $_XOR_ cell `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$194_CMP0.$xor$<stdcells.v>:808$983.Y [9] = $procdff$881.Q [9]'. |
| Replacing $_AND_ cell `$techmap$procmux$250.$and$<stdcells.v>:1203$1011.V[0].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$250.$and$<stdcells.v>:1203$1011.Y = $auto$opt_reduce.cc:127:opt_mux$909.buffer [9]'. |
| Replacing $_AND_ cell `$techmap$procmux$347.$and$<stdcells.v>:1203$1016.V[0].gate' (1?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$347.$and$<stdcells.v>:1203$1016.Y = $auto$opt_reduce.cc:127:opt_mux$915.buffer [6]'. |
| Replacing $_AND_ cell `$techmap$procmux$347.$and$<stdcells.v>:1203$1017.V[0].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$347.$and$<stdcells.v>:1203$1017.Y = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[0].gate' (1) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [0] = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[10].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [10] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[11].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [11] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[12].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [12] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[13].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [13] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[14].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [14] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[15].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [15] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[1].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [1] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[2].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [2] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[3].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [3] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[4].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [4] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[5].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [5] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[6].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [6] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[7].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [7] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[8].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [8] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.V[9].gate' (0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_bit_ctrl.v:224$11.$not$<stdcells.v>:942$1020.Y [9] = 1'1'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.gate1' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.gate2' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.t2 = $procdff$870.Q [0]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[10].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[10].adder.t1 = $procdff$870.Q [10]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[11].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[11].adder.t1 = $procdff$870.Q [11]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[12].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[12].adder.t1 = $procdff$870.Q [12]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[13].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[13].adder.t1 = $procdff$870.Q [13]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[14].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[14].adder.t1 = $procdff$870.Q [14]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[15].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[15].adder.t1 = $procdff$870.Q [15]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[1].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[1].adder.t1 = $procdff$870.Q [1]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[2].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[2].adder.t1 = $procdff$870.Q [2]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[3].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[3].adder.t1 = $procdff$870.Q [3]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[4].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[4].adder.t1 = $procdff$870.Q [4]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[5].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[5].adder.t1 = $procdff$870.Q [5]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[6].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[6].adder.t1 = $procdff$870.Q [6]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[7].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[7].adder.t1 = $procdff$870.Q [7]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[8].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[8].adder.t1 = $procdff$870.Q [8]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[9].adder.gate1' (?1) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[9].adder.t1 = $procdff$870.Q [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [1] = $techmap$procmux$155_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [10] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [11] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [10]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [12] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [11]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [1] = $techmap$procmux$153_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [2] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [3] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [4] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [3]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[5].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [5] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [4]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [6] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [7] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [6]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [8] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [7]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[9].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [9] = $techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [8]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1000.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.buffer [1] = $techmap$procmux$186_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1001.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1002.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1003.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1004.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.V[1].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.buffer [1] = $techmap$procmux$188_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1005.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1006.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1007.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$1008.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$993.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$994.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$995.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$996.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$998.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.V[1].gate' (00) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.buffer [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.buffer [2] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.buffer [3] = $techmap$procmux$185.$reduce_or$<stdcells.v>:1210$999.buffer [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$347.$reduce_or$<stdcells.v>:1210$1019.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$347.$reduce_or$<stdcells.v>:1210$1019.buffer [1] = $auto$opt_reduce.cc:127:opt_mux$915.buffer [6]'. |
| Replacing $_OR_ cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.gate5' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[0].adder.X = $procdff$870.Q [0]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$966.buffer [13] = $techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [0]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[12].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [12] = $techmap$procmux$183_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[11].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [11] = $techmap$procmux$181_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[10].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [10] = $techmap$procmux$179_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[9].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [9] = $techmap$procmux$177_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$971.buffer [13] = $techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [5]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[8].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [8] = $techmap$procmux$173_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[7].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [7] = $techmap$procmux$171_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[6].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [6] = $techmap$procmux$169_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$975.buffer [13] = $techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [9]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[5].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [5] = $techmap$procmux$165_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[4].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [4] = $techmap$procmux$163_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [3] = $techmap$procmux$161_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.V[13].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$979.buffer [13] = $techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [13]'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [2] = $techmap$procmux$157_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.V[3].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$992.buffer [3] = $techmap$procmux$192_CMP0.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.V[2].gate' (?0) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$reduce_or$<stdcells.v>:1210$997.buffer [2] = $techmap$eq$rtl/i2c_master_bit_ctrl.v:301$29.$not$<stdcells.v>:808$949.Y'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[10].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [10] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[11].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [11] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[12].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [12] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[14].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [14] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[15].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [15] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[16].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [16] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[1].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[2].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [2] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[3].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[4].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [4] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[6].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [6] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[7].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [7] = 1'0'. |
| Replacing $_MUX_ cell `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.V[8].gate' (00?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$185.$ternary$<stdcells.v>:1214$987.Y [8] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[10].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [10] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[11].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [11] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[12].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [12] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[14].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [14] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[15].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [15] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[16].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [16] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[1].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [1] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[2].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[3].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[4].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [4] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[6].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [6] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[7].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [7] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$152.$and$<stdcells.v>:1203$965.V[8].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$and$<stdcells.v>:1203$965.Y [8] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$967.buffer [13] = $techmap$procmux$183_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$968.buffer [13] = $techmap$procmux$181_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$969.buffer [13] = $techmap$procmux$179_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$970.buffer [13] = $techmap$procmux$177_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$972.buffer [13] = $techmap$procmux$173_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$973.buffer [13] = $techmap$procmux$171_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$974.buffer [13] = $techmap$procmux$169_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$976.buffer [13] = $techmap$procmux$165_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$977.buffer [13] = $techmap$procmux$163_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$978.buffer [13] = $techmap$procmux$161_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$980.buffer [13] = $techmap$procmux$157_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$981.buffer [13] = $techmap$procmux$155_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.V[13].gate' (0?) in module `\i2c_master_bit_ctrl' with constant driver `$techmap$procmux$152.$reduce_or$<stdcells.v>:1210$982.buffer [13] = $techmap$procmux$153_CMP0.$not$<stdcells.v>:808$985.Y'. |
| Replacing $_MUX_ cell `$procmux$454.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$454.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$454.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$454.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$454.V[2].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$454.Y [2] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$454.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$454.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$462.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$462.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$462.V[2].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$462.Y [2] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$462.V[4].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$462.Y [4] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$470.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$470.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$470.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$470.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$470.V[4].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$470.Y [4] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$478.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$478.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$478.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$478.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$478.V[4].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$478.Y [4] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$486.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$486.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$486.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$486.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$486.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$486.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$552.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$552.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$552.V[2].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$552.Y [2] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$552.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$552.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$560.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$560.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$560.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$560.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$568.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$568.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$568.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$568.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$576.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$576.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$576.V[1].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$576.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$584.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$584.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$584.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$584.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.gate3' (?1) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.t3 = $sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.t2'. |
| Replacing $_XOR_ cell `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.V[0].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.Y [0] = $procdff$889.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.V[1].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.Y [1] = $procdff$889.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.V[2].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.Y [2] = $procdff$889.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.V[4].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$415_CMP0.$xor$<stdcells.v>:808$1021.Y [4] = $procdff$889.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.V[0].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.Y [0] = $procdff$889.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.V[2].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.Y [2] = $procdff$889.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.V[3].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.Y [3] = $procdff$889.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.V[4].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$421_CMP0.$xor$<stdcells.v>:808$1021.Y [4] = $procdff$889.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.V[0].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.Y [0] = $procdff$889.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.V[1].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.Y [1] = $procdff$889.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.V[3].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.Y [3] = $procdff$889.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.V[4].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$427_CMP0.$xor$<stdcells.v>:808$1021.Y [4] = $procdff$889.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.V[1].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.Y [1] = $procdff$889.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.V[2].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.Y [2] = $procdff$889.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.V[3].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.Y [3] = $procdff$889.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.V[4].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$433_CMP0.$xor$<stdcells.v>:808$1021.Y [4] = $procdff$889.Q [4]'. |
| Replacing $_XOR_ cell `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.V[0].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.Y [0] = $procdff$889.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.V[1].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.Y [1] = $procdff$889.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.V[2].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.Y [2] = $procdff$889.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.V[3].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.Y [3] = $procdff$889.Q [3]'. |
| Replacing $_XOR_ cell `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.V[4].gate' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$443_CMP0.$xor$<stdcells.v>:808$1021.Y [4] = $procdff$889.Q [4]'. |
| Replacing $_AND_ cell `$techmap$procmux$512.$and$<stdcells.v>:1203$1012.V[0].gate' (0?) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$512.$and$<stdcells.v>:1203$1012.Y = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.V[0].gate' (1) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.Y [0] = 1'0'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.V[1].gate' (0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.Y [1] = 1'1'. |
| Replacing $_INV_ cell `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.V[2].gate' (0) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$sub$rtl/i2c_master_byte_ctrl.v:196$54.$not$<stdcells.v>:942$1047.Y [2] = 1'1'. |
| Replacing $_MUX_ cell `$procmux$489.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$489.Y [0] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$489.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$489.Y [3] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$587.V[0].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$587.Y [0] = 1'0'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.gate1' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.gate2' (?0) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.t2 = $procdff$887.Q [0]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[1].adder.gate1' (?1) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[1].adder.t1 = $procdff$887.Q [1]'. |
| Replacing $_AND_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[2].adder.gate1' (?1) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[2].adder.t1 = $procdff$887.Q [2]'. |
| Replacing $_OR_ cell `$techmap$procmux$512.$reduce_or$<stdcells.v>:1210$1013.V[1].gate' (0?) in module `\i2c_master_byte_ctrl' with constant driver `$techmap$procmux$512.$reduce_or$<stdcells.v>:1210$1013.buffer [1] = $techmap$procmux$512.$and$<stdcells.v>:1203$1011.Y'. |
| Replacing $_MUX_ cell `$procmux$492.V[3].gate' (00?) in module `\i2c_master_byte_ctrl' with constant driver `$procmux$492.Y [3] = 1'0'. |
| Replacing $_OR_ cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.gate5' (0?) in module `\i2c_master_byte_ctrl' with constant driver `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[0].adder.X = $procdff$887.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.V[0].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.Y [0] = \wb_adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.V[1].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.Y [1] = \wb_adr_i [1]'. |
| Replacing $_AND_ cell `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.V[2].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.Y [2] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.V[3].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.Y [3] = 1'0'. |
| Replacing $_AND_ cell `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.V[4].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$and$<stdcells.v>:1203$1055.Y [4] = 1'0'. |
| Replacing $_XOR_ cell `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.Y [0] = \wb_adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.Y [1] = \wb_adr_i [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = \wb_adr_i [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.Y [0] = \wb_adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = \wb_adr_i [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.Y [1] = \wb_adr_i [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = \wb_adr_i [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.Y [0] = \wb_adr_i [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.Y [1] = \wb_adr_i [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' (?0) in module `\i2c_master_top' with constant driver `$techmap$procmux$740_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = \wb_adr_i [2]'. |
| Replacing $_XOR_ cell `$xor$rtl/i2c_master_top.v:157$60.V[0].gate' (?0) in module `\i2c_master_top' with constant driver `$xor$rtl/i2c_master_top.v:157$60.Y = \arst_i'. |
| Replacing $_OR_ cell `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1062.V[2].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1062.buffer [2] = $techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1062.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1063.V[2].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1063.buffer [2] = $techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1063.buffer [1]'. |
| Replacing $_OR_ cell `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1064.V[2].gate' (0?) in module `\i2c_master_top' with constant driver `$techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1064.buffer [2] = $techmap$procmux$727.$reduce_or$<stdcells.v>:1210$1064.buffer [1]'. |
| |
| 11.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Cell `$auto$opt_reduce.cc:127:opt_mux$909.V[1].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[1].gate'. |
| Redirecting output \Y: $auto$opt_reduce.cc:127:opt_mux$909.buffer [1] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [1] |
| Removing $_OR_ cell `$auto$opt_reduce.cc:127:opt_mux$909.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$auto$opt_reduce.cc:127:opt_mux$913.V[1].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[1].gate'. |
| Redirecting output \Y: $auto$opt_reduce.cc:127:opt_mux$913.buffer [1] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [1] |
| Removing $_OR_ cell `$auto$opt_reduce.cc:127:opt_mux$913.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[1].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [1] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[2].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [2] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[3].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [3] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[4].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [4] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[5].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [5] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[6].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [6] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[7].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [7] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[8].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [8] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[9].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [9] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$163_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$165_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$167_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$169_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$171_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$173_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$175_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$177_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$179_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$179_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$179_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$948.V[1].gate' is identical to cell `$techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$948.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$948.buffer [1] = $techmap$procmux$186_CMP0.$reduce_or$<stdcells.v>:808$948.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$188_CMP0.$reduce_or$<stdcells.v>:808$948.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [1] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[1].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [2] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[2].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [3] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[3].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [4] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[4].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[5].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [5] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [5] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[5].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[6].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [6] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [6] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[6].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[7].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [7] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [7] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[7].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[8].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [8] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [8] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[8].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[9].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [9] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [9] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[9].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[10].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [10] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[11].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [11] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[12].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[12].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [12] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [12] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[12].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[13].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$907.V[13].gate'. |
| Redirecting output \Y: $techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.buffer [13] = $auto$opt_reduce.cc:127:opt_mux$907.buffer [13] |
| Removing $_OR_ cell `$techmap$procmux$152.$reduce_or$<stdcells.v>:1214$950.V[13].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [11] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[12].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [12] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [12] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[13].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [13] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [13] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[14].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[14].gate'. |
| Redirecting output \Y: $techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [14] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [14] |
| Removing $_OR_ cell `$techmap$procmux$153_CMP0.$reduce_or$<stdcells.v>:808$984.V[14].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [11] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[12].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [12] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [12] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[13].gate'. |
| Redirecting output \Y: $techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [13] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [13] |
| Removing $_OR_ cell `$techmap$procmux$155_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [11] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[12].gate'. |
| Redirecting output \Y: $techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [12] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [12] |
| Removing $_OR_ cell `$techmap$procmux$157_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [11] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$159_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$161_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[10].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [10] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [10] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[10].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[11].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [11] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [11] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[11].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[12].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [12] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [12] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[12].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[13].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [13] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [13] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[13].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[14].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[14].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [14] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [14] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[14].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[15].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[15].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [15] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [15] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[15].gate' from module `\i2c_master_bit_ctrl'. |
| Cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[16].gate' is identical to cell `$reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.V[16].gate'. |
| Redirecting output \Y: $techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.buffer [16] = $reduce_or$rtl/i2c_master_bit_ctrl.v:309$35.buffer [16] |
| Removing $_OR_ cell `$techmap$procmux$194_CMP0.$reduce_or$<stdcells.v>:808$984.V[16].gate' from module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$456.V[0].gate' is identical to cell `$procmux$449.V[0].gate'. |
| Redirecting output \Y: $procmux$456.Y [0] = $procmux$449.Y [0] |
| Removing $_MUX_ cell `$procmux$456.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$456.V[1].gate' is identical to cell `$procmux$449.V[1].gate'. |
| Redirecting output \Y: $procmux$456.Y [1] = $procmux$449.Y [1] |
| Removing $_MUX_ cell `$procmux$456.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$456.V[2].gate' is identical to cell `$procmux$449.V[2].gate'. |
| Redirecting output \Y: $procmux$456.Y [2] = $procmux$449.Y [2] |
| Removing $_MUX_ cell `$procmux$456.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$456.V[3].gate' is identical to cell `$procmux$449.V[3].gate'. |
| Redirecting output \Y: $procmux$456.Y [3] = $procmux$449.Y [3] |
| Removing $_MUX_ cell `$procmux$456.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$464.V[0].gate' is identical to cell `$procmux$449.V[0].gate'. |
| Redirecting output \Y: $procmux$464.Y [0] = $procmux$449.Y [0] |
| Removing $_MUX_ cell `$procmux$464.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$464.V[2].gate' is identical to cell `$procmux$449.V[2].gate'. |
| Redirecting output \Y: $procmux$464.Y [2] = $procmux$449.Y [2] |
| Removing $_MUX_ cell `$procmux$464.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$464.V[4].gate' is identical to cell `$procmux$449.V[4].gate'. |
| Redirecting output \Y: $procmux$464.Y [4] = $procmux$449.Y [4] |
| Removing $_MUX_ cell `$procmux$464.V[4].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$470.V[2].gate' is identical to cell `$procmux$462.V[1].gate'. |
| Redirecting output \Y: $procmux$470.Y [2] = $procmux$462.Y [1] |
| Removing $_MUX_ cell `$procmux$470.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$470.V[3].gate' is identical to cell `$procmux$462.V[3].gate'. |
| Redirecting output \Y: $procmux$470.Y [3] = $procmux$462.Y [3] |
| Removing $_MUX_ cell `$procmux$470.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$472.V[0].gate' is identical to cell `$procmux$449.V[0].gate'. |
| Redirecting output \Y: $procmux$472.Y [0] = $procmux$449.Y [0] |
| Removing $_MUX_ cell `$procmux$472.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$472.V[1].gate' is identical to cell `$procmux$449.V[1].gate'. |
| Redirecting output \Y: $procmux$472.Y [1] = $procmux$449.Y [1] |
| Removing $_MUX_ cell `$procmux$472.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$472.V[3].gate' is identical to cell `$procmux$464.V[3].gate'. |
| Redirecting output \Y: $procmux$472.Y [3] = $procmux$464.Y [3] |
| Removing $_MUX_ cell `$procmux$472.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$472.V[4].gate' is identical to cell `$procmux$449.V[4].gate'. |
| Redirecting output \Y: $procmux$472.Y [4] = $procmux$449.Y [4] |
| Removing $_MUX_ cell `$procmux$472.V[4].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$480.V[0].gate' is identical to cell `$procmux$449.V[0].gate'. |
| Redirecting output \Y: $procmux$480.Y [0] = $procmux$449.Y [0] |
| Removing $_MUX_ cell `$procmux$480.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$480.V[3].gate' is identical to cell `$procmux$449.V[3].gate'. |
| Redirecting output \Y: $procmux$480.Y [3] = $procmux$449.Y [3] |
| Removing $_MUX_ cell `$procmux$480.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$480.V[4].gate' is identical to cell `$procmux$449.V[4].gate'. |
| Redirecting output \Y: $procmux$480.Y [4] = $procmux$449.Y [4] |
| Removing $_MUX_ cell `$procmux$480.V[4].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$489.V[1].gate' is identical to cell `$procmux$478.V[1].gate'. |
| Redirecting output \Y: $procmux$489.Y [1] = $procmux$478.Y [1] |
| Removing $_MUX_ cell `$procmux$489.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$552.V[1].gate' is identical to cell `$procmux$454.V[4].gate'. |
| Redirecting output \Y: $procmux$552.Y [1] = $procmux$454.Y [4] |
| Removing $_MUX_ cell `$procmux$552.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$554.V[0].gate' is identical to cell `$procmux$547.V[0].gate'. |
| Redirecting output \Y: $procmux$554.Y [0] = $procmux$547.Y [0] |
| Removing $_MUX_ cell `$procmux$554.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$554.V[2].gate' is identical to cell `$procmux$547.V[2].gate'. |
| Redirecting output \Y: $procmux$554.Y [2] = $procmux$547.Y [2] |
| Removing $_MUX_ cell `$procmux$554.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$554.V[3].gate' is identical to cell `$procmux$547.V[3].gate'. |
| Redirecting output \Y: $procmux$554.Y [3] = $procmux$547.Y [3] |
| Removing $_MUX_ cell `$procmux$554.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$560.V[2].gate' is identical to cell `$procmux$462.V[3].gate'. |
| Redirecting output \Y: $procmux$560.Y [2] = $procmux$462.Y [3] |
| Removing $_MUX_ cell `$procmux$560.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$560.V[3].gate' is identical to cell `$procmux$462.V[1].gate'. |
| Redirecting output \Y: $procmux$560.Y [3] = $procmux$462.Y [1] |
| Removing $_MUX_ cell `$procmux$560.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$562.V[0].gate' is identical to cell `$procmux$547.V[0].gate'. |
| Redirecting output \Y: $procmux$562.Y [0] = $procmux$547.Y [0] |
| Removing $_MUX_ cell `$procmux$562.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$562.V[1].gate' is identical to cell `$procmux$547.V[1].gate'. |
| Redirecting output \Y: $procmux$562.Y [1] = $procmux$547.Y [1] |
| Removing $_MUX_ cell `$procmux$562.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$568.V[2].gate' is identical to cell `$procmux$462.V[1].gate'. |
| Redirecting output \Y: $procmux$568.Y [2] = $procmux$462.Y [1] |
| Removing $_MUX_ cell `$procmux$568.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$568.V[3].gate' is identical to cell `$procmux$462.V[3].gate'. |
| Redirecting output \Y: $procmux$568.Y [3] = $procmux$462.Y [3] |
| Removing $_MUX_ cell `$procmux$568.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$570.V[0].gate' is identical to cell `$procmux$547.V[0].gate'. |
| Redirecting output \Y: $procmux$570.Y [0] = $procmux$547.Y [0] |
| Removing $_MUX_ cell `$procmux$570.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$570.V[1].gate' is identical to cell `$procmux$547.V[1].gate'. |
| Redirecting output \Y: $procmux$570.Y [1] = $procmux$547.Y [1] |
| Removing $_MUX_ cell `$procmux$570.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$576.V[2].gate' is identical to cell `$procmux$478.V[2].gate'. |
| Redirecting output \Y: $procmux$576.Y [2] = $procmux$478.Y [2] |
| Removing $_MUX_ cell `$procmux$576.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$576.V[3].gate' is identical to cell `$procmux$478.V[1].gate'. |
| Redirecting output \Y: $procmux$576.Y [3] = $procmux$478.Y [1] |
| Removing $_MUX_ cell `$procmux$576.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$578.V[0].gate' is identical to cell `$procmux$547.V[0].gate'. |
| Redirecting output \Y: $procmux$578.Y [0] = $procmux$547.Y [0] |
| Removing $_MUX_ cell `$procmux$578.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$578.V[1].gate' is identical to cell `$procmux$547.V[1].gate'. |
| Redirecting output \Y: $procmux$578.Y [1] = $procmux$547.Y [1] |
| Removing $_MUX_ cell `$procmux$578.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$584.V[1].gate' is identical to cell `$procmux$486.V[4].gate'. |
| Redirecting output \Y: $procmux$584.Y [1] = $procmux$486.Y [4] |
| Removing $_MUX_ cell `$procmux$584.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$584.V[2].gate' is identical to cell `$procmux$486.V[2].gate'. |
| Redirecting output \Y: $procmux$584.Y [2] = $procmux$486.Y [2] |
| Removing $_MUX_ cell `$procmux$584.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$587.V[1].gate' is identical to cell `$procmux$489.V[4].gate'. |
| Redirecting output \Y: $procmux$587.Y [1] = $procmux$489.Y [4] |
| Removing $_MUX_ cell `$procmux$587.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$587.V[2].gate' is identical to cell `$procmux$489.V[2].gate'. |
| Redirecting output \Y: $procmux$587.Y [2] = $procmux$489.Y [2] |
| Removing $_MUX_ cell `$procmux$587.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$587.V[3].gate' is identical to cell `$procmux$478.V[1].gate'. |
| Redirecting output \Y: $procmux$587.Y [3] = $procmux$478.Y [1] |
| Removing $_MUX_ cell `$procmux$587.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$590.V[0].gate' is identical to cell `$procmux$492.V[0].gate'. |
| Redirecting output \Y: $procmux$590.Y [0] = $procmux$492.Y [0] |
| Removing $_MUX_ cell `$procmux$590.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$590.V[1].gate' is identical to cell `$procmux$492.V[4].gate'. |
| Redirecting output \Y: $procmux$590.Y [1] = $procmux$492.Y [4] |
| Removing $_MUX_ cell `$procmux$590.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$590.V[2].gate' is identical to cell `$procmux$492.V[2].gate'. |
| Redirecting output \Y: $procmux$590.Y [2] = $procmux$492.Y [2] |
| Removing $_MUX_ cell `$procmux$590.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$590.V[3].gate' is identical to cell `$procmux$492.V[1].gate'. |
| Redirecting output \Y: $procmux$590.Y [3] = $procmux$492.Y [1] |
| Removing $_MUX_ cell `$procmux$590.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$procmux$700.V[0].gate' is identical to cell `$procmux$462.V[1].gate'. |
| Redirecting output \Y: $procmux$700.Y = $procmux$462.Y [1] |
| Removing $_MUX_ cell `$procmux$700.V[0].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$427_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate' is identical to cell `$techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$427_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [1] = $techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$427_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate' is identical to cell `$techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [1] = $techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.V[2].gate' is identical to cell `$techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [2] = $techmap$procmux$415_CMP0.$reduce_or$<stdcells.v>:808$1022.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$443_CMP0.$reduce_or$<stdcells.v>:808$1022.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[1].gate' is identical to cell `$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.buffer [1] = $techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[2].gate' is identical to cell `$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.buffer [2] = $techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.buffer [2] |
| Removing $_OR_ cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[2].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[3].gate' is identical to cell `$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.V[3].gate'. |
| Redirecting output \Y: $techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.buffer [3] = $techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.buffer [3] |
| Removing $_OR_ cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[3].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[4].gate' is identical to cell `$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.V[4].gate'. |
| Redirecting output \Y: $techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.buffer [4] = $techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.buffer [4] |
| Removing $_OR_ cell `$techmap$procmux$556.$reduce_or$<stdcells.v>:1214$1036.V[4].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$608.$reduce_or$<stdcells.v>:1214$1009.V[1].gate' is identical to cell `$techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$608.$reduce_or$<stdcells.v>:1214$1009.buffer [1] = $techmap$procmux$458.$reduce_or$<stdcells.v>:1214$1024.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$608.$reduce_or$<stdcells.v>:1214$1009.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Cell `$techmap$procmux$696.$reduce_or$<stdcells.v>:1214$1009.V[1].gate' is identical to cell `$auto$opt_reduce.cc:127:opt_mux$919.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$696.$reduce_or$<stdcells.v>:1214$1009.buffer [1] = $auto$opt_reduce.cc:127:opt_mux$919.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$696.$reduce_or$<stdcells.v>:1214$1009.V[1].gate' from module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Cell `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' is identical to cell `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = $techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.Y [2] |
| Removing $_XOR_ cell `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' is identical to cell `$techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.V[2].gate'. |
| Redirecting output \Y: $techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.Y [2] = $techmap$eq$rtl/i2c_master_top.v:213$72.$xor$<stdcells.v>:808$1048.Y [2] |
| Removing $_XOR_ cell `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.V[2].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' is identical to cell `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.Y [0] = $techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' is identical to cell `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.Y [1] = $techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$734_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' is identical to cell `$techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.Y [1] = $techmap$procmux$728_CMP0.$xor$<stdcells.v>:808$1048.Y [1] |
| Removing $_XOR_ cell `$techmap$procmux$736_CMP0.$xor$<stdcells.v>:808$1048.V[1].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' is identical to cell `$techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.Y [0] = $techmap$procmux$730_CMP0.$xor$<stdcells.v>:808$1048.Y [0] |
| Removing $_XOR_ cell `$techmap$procmux$738_CMP0.$xor$<stdcells.v>:808$1048.V[0].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$740_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' is identical to cell `$techmap$eq$rtl/i2c_master_top.v:213$72.$reduce_or$<stdcells.v>:808$1049.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$740_CMP0.$reduce_or$<stdcells.v>:808$1049.buffer [1] = $techmap$eq$rtl/i2c_master_top.v:213$72.$reduce_or$<stdcells.v>:808$1049.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$740_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$736_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' is identical to cell `$techmap$procmux$728_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$736_CMP0.$reduce_or$<stdcells.v>:808$1049.buffer [1] = $techmap$procmux$728_CMP0.$reduce_or$<stdcells.v>:808$1049.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$736_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' from module `\i2c_master_top'. |
| Cell `$techmap$procmux$738_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' is identical to cell `$techmap$procmux$730_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate'. |
| Redirecting output \Y: $techmap$procmux$738_CMP0.$reduce_or$<stdcells.v>:808$1049.buffer [1] = $techmap$procmux$730_CMP0.$reduce_or$<stdcells.v>:808$1049.buffer [1] |
| Removing $_OR_ cell `$techmap$procmux$738_CMP0.$reduce_or$<stdcells.v>:808$1049.V[1].gate' from module `\i2c_master_top'. |
| Removed a total of 198 cells. |
| |
| 11.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| Optimizing cells in module \i2c_master_top. |
| Performed a total of 0 changes. |
| |
| 11.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 11.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 11.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| removing unused `$_AND_' cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[15].adder.gate3'. |
| removing unused `$_OR_' cell `$sub$rtl/i2c_master_bit_ctrl.v:224$11.alu.V[15].adder.gate5'. |
| removed 1494 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| removing unused `$_AND_' cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[2].adder.gate3'. |
| removing unused `$_OR_' cell `$sub$rtl/i2c_master_byte_ctrl.v:196$54.alu.V[2].adder.gate5'. |
| removed 775 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_top.. |
| removed 585 unused temporary wires. |
| |
| 11.9. Executing OPT_CONST pass (perform const folding). |
| |
| 11.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 11.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| Optimizing cells in module \i2c_master_top. |
| Performed a total of 0 changes. |
| |
| 11.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 11.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 11.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| Finding unused cells or wires in module \i2c_master_top.. |
| |
| 11.16. Executing OPT_CONST pass (perform const folding). |
| |
| 11.17. Optimizing in-memory representation of design. |
| |
| 11.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 12. Executing ABC pass (technology mapping using ABC). |
| |
| 12.1. Extracting gate logic of module `\i2c_master_bit_ctrl' to `/tmp/yosys-abc-Y0i9to/input.v'.. |
| Extracted 493 gates and 568 wires to a logic network with 73 inputs and 48 outputs. |
| |
| 12.1.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-Y0i9to/input.v; read_library /tmp/yosys-abc-Y0i9to/stdcells.genlib; map; write_verilog /tmp/yosys-abc-Y0i9to/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-Y0i9to/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-Y0i9to/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-Y0i9to/stdcells.super". Time = 0.00 sec |
| |
| 12.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 242 |
| ABC RESULTS: INV cells: 66 |
| ABC RESULTS: MUX cells: 38 |
| ABC RESULTS: OR cells: 78 |
| ABC RESULTS: XOR cells: 15 |
| ABC RESULTS: internal signals: 447 |
| ABC RESULTS: input signals: 73 |
| ABC RESULTS: output signals: 48 |
| |
| 12.1.3. Removing temp directory `/tmp/yosys-abc-Y0i9to': |
| Removing `/tmp/yosys-abc-Y0i9to/input.v'. |
| Removing `/tmp/yosys-abc-Y0i9to/output.v'. |
| Removing `/tmp/yosys-abc-Y0i9to/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-Y0i9to/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-Y0i9to/stdcells.super'. |
| Removing `/tmp/yosys-abc-Y0i9to'. |
| |
| 12.2. Extracting gate logic of module `\i2c_master_byte_ctrl' to `/tmp/yosys-abc-HQsi4F/input.v'.. |
| Extracted 254 gates and 297 wires to a logic network with 41 inputs and 25 outputs. |
| |
| 12.2.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-HQsi4F/input.v; read_library /tmp/yosys-abc-HQsi4F/stdcells.genlib; map; write_verilog /tmp/yosys-abc-HQsi4F/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-HQsi4F/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-HQsi4F/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-HQsi4F/stdcells.super". Time = 0.00 sec |
| |
| 12.2.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 103 |
| ABC RESULTS: INV cells: 23 |
| ABC RESULTS: MUX cells: 53 |
| ABC RESULTS: OR cells: 39 |
| ABC RESULTS: XOR cells: 3 |
| ABC RESULTS: internal signals: 231 |
| ABC RESULTS: input signals: 41 |
| ABC RESULTS: output signals: 25 |
| |
| 12.2.3. Removing temp directory `/tmp/yosys-abc-HQsi4F': |
| Removing `/tmp/yosys-abc-HQsi4F/input.v'. |
| Removing `/tmp/yosys-abc-HQsi4F/output.v'. |
| Removing `/tmp/yosys-abc-HQsi4F/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-HQsi4F/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-HQsi4F/stdcells.super'. |
| Removing `/tmp/yosys-abc-HQsi4F'. |
| |
| 12.3. Extracting gate logic of module `\i2c_master_top' to `/tmp/yosys-abc-FdkwcY/input.v'.. |
| Extracted 276 gates and 350 wires to a logic network with 72 inputs and 54 outputs. |
| |
| 12.3.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-FdkwcY/input.v; read_library /tmp/yosys-abc-FdkwcY/stdcells.genlib; map; write_verilog /tmp/yosys-abc-FdkwcY/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-FdkwcY/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-FdkwcY/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-FdkwcY/stdcells.super". Time = 0.00 sec |
| |
| 12.3.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 112 |
| ABC RESULTS: INV cells: 10 |
| ABC RESULTS: MUX cells: 77 |
| ABC RESULTS: OR cells: 71 |
| ABC RESULTS: internal signals: 224 |
| ABC RESULTS: input signals: 72 |
| ABC RESULTS: output signals: 54 |
| |
| 12.3.3. Removing temp directory `/tmp/yosys-abc-FdkwcY': |
| Removing `/tmp/yosys-abc-FdkwcY/input.v'. |
| Removing `/tmp/yosys-abc-FdkwcY/output.v'. |
| Removing `/tmp/yosys-abc-FdkwcY/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-FdkwcY/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-FdkwcY/stdcells.super'. |
| Removing `/tmp/yosys-abc-FdkwcY'. |
| |
| 13. Executing OPT pass (performing simple optimizations). |
| |
| 13.1. Optimizing in-memory representation of design. |
| |
| 13.2. Executing OPT_CONST pass (perform const folding). |
| |
| 13.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 13.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \i2c_master_bit_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_byte_ctrl.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \i2c_master_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 13.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \i2c_master_bit_ctrl. |
| Optimizing cells in module \i2c_master_byte_ctrl. |
| Optimizing cells in module \i2c_master_top. |
| Performed a total of 0 changes. |
| |
| 13.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\i2c_master_bit_ctrl'. |
| Finding identical cells in module `\i2c_master_byte_ctrl'. |
| Finding identical cells in module `\i2c_master_top'. |
| Removed a total of 0 cells. |
| |
| 13.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 13.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \i2c_master_bit_ctrl.. |
| removing unused non-port wire \slave_wait. |
| removed 294 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_byte_ctrl.. |
| removing unused non-port wire \cnt_done. |
| removing unused non-port wire \go. |
| removed 152 unused temporary wires. |
| Finding unused cells or wires in module \i2c_master_top.. |
| removing unused non-port wire \wb_wacc. |
| removed 184 unused temporary wires. |
| |
| 13.9. Executing OPT_CONST pass (perform const folding). |
| |
| 13.10. Optimizing in-memory representation of design. |
| |
| 13.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 14. Executing Verilog backend. |
| Full command line: write_verilog -noattr output/synth.v |
| Dumping module `\i2c_master_bit_ctrl'. |
| renaming `$0\al[0:0]' to `_000_'. |
| renaming `$0\busy[0:0]' to `_001_'. |
| renaming `$0\c_state[16:0]' to `_002_'. |
| renaming `$0\clk_en[0:0]' to `_003_'. |
| renaming `$0\cmd_ack[0:0]' to `_004_'. |
| renaming `$0\cmd_stop[0:0]' to `_005_'. |
| renaming `$0\cnt[15:0]' to `_006_'. |
| renaming `$0\dSCL[0:0]' to `_007_'. |
| renaming `$0\dSDA[0:0]' to `_008_'. |
| renaming `$0\dout[0:0]' to `_009_'. |
| renaming `$0\sSCL[0:0]' to `_010_'. |
| renaming `$0\sSDA[0:0]' to `_011_'. |
| renaming `$0\scl_oen[0:0]' to `_012_'. |
| renaming `$0\sda_chk[0:0]' to `_013_'. |
| renaming `$0\sda_oen[0:0]' to `_014_'. |
| renaming `$0\sta_condition[0:0]' to `_015_'. |
| renaming `$0\sto_condition[0:0]' to `_016_'. |
| renaming `$abc$1068$g000' to `_408_'. |
| renaming `$abc$1068$g001' to `_409_'. |
| renaming `$abc$1068$g002' to `_410_'. |
| renaming `$abc$1068$g003' to `_411_'. |
| renaming `$abc$1068$g004' to `_412_'. |
| renaming `$abc$1068$g005' to `_413_'. |
| renaming `$abc$1068$g006' to `_414_'. |
| renaming `$abc$1068$g007' to `_415_'. |
| renaming `$abc$1068$g008' to `_416_'. |
| renaming `$abc$1068$g009' to `_417_'. |
| renaming `$abc$1068$g010' to `_418_'. |
| renaming `$abc$1068$g011' to `_419_'. |
| renaming `$abc$1068$g012' to `_420_'. |
| renaming `$abc$1068$g013' to `_421_'. |
| renaming `$abc$1068$g014' to `_422_'. |
| renaming `$abc$1068$g015' to `_423_'. |
| renaming `$abc$1068$g016' to `_424_'. |
| renaming `$abc$1068$g017' to `_425_'. |
| renaming `$abc$1068$g018' to `_426_'. |
| renaming `$abc$1068$g019' to `_427_'. |
| renaming `$abc$1068$g020' to `_428_'. |
| renaming `$abc$1068$g021' to `_429_'. |
| renaming `$abc$1068$g022' to `_430_'. |
| renaming `$abc$1068$g023' to `_431_'. |
| renaming `$abc$1068$g024' to `_432_'. |
| renaming `$abc$1068$g025' to `_433_'. |
| renaming `$abc$1068$g026' to `_434_'. |
| renaming `$abc$1068$g027' to `_435_'. |
| renaming `$abc$1068$g028' to `_436_'. |
| renaming `$abc$1068$g029' to `_437_'. |
| renaming `$abc$1068$g030' to `_438_'. |
| renaming `$abc$1068$g031' to `_439_'. |
| renaming `$abc$1068$g032' to `_440_'. |
| renaming `$abc$1068$g033' to `_441_'. |
| renaming `$abc$1068$g034' to `_442_'. |
| renaming `$abc$1068$g035' to `_443_'. |
| renaming `$abc$1068$g036' to `_444_'. |
| renaming `$abc$1068$g037' to `_445_'. |
| renaming `$abc$1068$g038' to `_446_'. |
| renaming `$abc$1068$g039' to `_447_'. |
| renaming `$abc$1068$g040' to `_448_'. |
| renaming `$abc$1068$g041' to `_449_'. |
| renaming `$abc$1068$g042' to `_450_'. |
| renaming `$abc$1068$g043' to `_451_'. |
| renaming `$abc$1068$g044' to `_452_'. |
| renaming `$abc$1068$g045' to `_453_'. |
| renaming `$abc$1068$g046' to `_454_'. |
| renaming `$abc$1068$g047' to `_455_'. |
| renaming `$abc$1068$g048' to `_456_'. |
| renaming `$abc$1068$g049' to `_457_'. |
| renaming `$abc$1068$g050' to `_458_'. |
| renaming `$abc$1068$g051' to `_459_'. |
| renaming `$abc$1068$g052' to `_460_'. |
| renaming `$abc$1068$g053' to `_461_'. |
| renaming `$abc$1068$g054' to `_462_'. |
| renaming `$abc$1068$g055' to `_463_'. |
| renaming `$abc$1068$g056' to `_464_'. |
| renaming `$abc$1068$g057' to `_465_'. |
| renaming `$abc$1068$g058' to `_466_'. |
| renaming `$abc$1068$g059' to `_467_'. |
| renaming `$abc$1068$g060' to `_468_'. |
| renaming `$abc$1068$g061' to `_469_'. |
| renaming `$abc$1068$g062' to `_470_'. |
| renaming `$abc$1068$g063' to `_471_'. |
| renaming `$abc$1068$g064' to `_472_'. |
| renaming `$abc$1068$g065' to `_473_'. |
| renaming `$abc$1068$g066' to `_474_'. |
| renaming `$abc$1068$g067' to `_475_'. |
| renaming `$abc$1068$g068' to `_476_'. |
| renaming `$abc$1068$g069' to `_477_'. |
| renaming `$abc$1068$g070' to `_478_'. |
| renaming `$abc$1068$g071' to `_479_'. |
| renaming `$abc$1068$g072' to `_480_'. |
| renaming `$abc$1068$g073' to `_481_'. |
| renaming `$abc$1068$g074' to `_482_'. |
| renaming `$abc$1068$g075' to `_483_'. |
| renaming `$abc$1068$g076' to `_484_'. |
| renaming `$abc$1068$g077' to `_485_'. |
| renaming `$abc$1068$g078' to `_486_'. |
| renaming `$abc$1068$g079' to `_487_'. |
| renaming `$abc$1068$g080' to `_488_'. |
| renaming `$abc$1068$g081' to `_489_'. |
| renaming `$abc$1068$g082' to `_490_'. |
| renaming `$abc$1068$g083' to `_491_'. |
| renaming `$abc$1068$g084' to `_492_'. |
| renaming `$abc$1068$g085' to `_493_'. |
| renaming `$abc$1068$g086' to `_494_'. |
| renaming `$abc$1068$g087' to `_495_'. |
| renaming `$abc$1068$g088' to `_496_'. |
| renaming `$abc$1068$g089' to `_497_'. |
| renaming `$abc$1068$g090' to `_498_'. |
| renaming `$abc$1068$g091' to `_499_'. |
| renaming `$abc$1068$g092' to `_500_'. |
| renaming `$abc$1068$g093' to `_501_'. |
| renaming `$abc$1068$g094' to `_502_'. |
| renaming `$abc$1068$g095' to `_503_'. |
| renaming `$abc$1068$g096' to `_504_'. |
| renaming `$abc$1068$g097' to `_505_'. |
| renaming `$abc$1068$g098' to `_506_'. |
| renaming `$abc$1068$g099' to `_507_'. |
| renaming `$abc$1068$g100' to `_508_'. |
| renaming `$abc$1068$g101' to `_509_'. |
| renaming `$abc$1068$g102' to `_510_'. |
| renaming `$abc$1068$g103' to `_511_'. |
| renaming `$abc$1068$g104' to `_512_'. |
| renaming `$abc$1068$g105' to `_513_'. |
| renaming `$abc$1068$g106' to `_514_'. |
| renaming `$abc$1068$g107' to `_515_'. |
| renaming `$abc$1068$g108' to `_516_'. |
| renaming `$abc$1068$g109' to `_517_'. |
| renaming `$abc$1068$g110' to `_518_'. |
| renaming `$abc$1068$g111' to `_519_'. |
| renaming `$abc$1068$g112' to `_520_'. |
| renaming `$abc$1068$g113' to `_521_'. |
| renaming `$abc$1068$g114' to `_522_'. |
| renaming `$abc$1068$g115' to `_523_'. |
| renaming `$abc$1068$g116' to `_524_'. |
| renaming `$abc$1068$g117' to `_525_'. |
| renaming `$abc$1068$g118' to `_526_'. |
| renaming `$abc$1068$g119' to `_527_'. |
| renaming `$abc$1068$g120' to `_528_'. |
| renaming `$abc$1068$g121' to `_529_'. |
| renaming `$abc$1068$g122' to `_530_'. |
| renaming `$abc$1068$g123' to `_531_'. |
| renaming `$abc$1068$g124' to `_532_'. |
| renaming `$abc$1068$g125' to `_533_'. |
| renaming `$abc$1068$g126' to `_534_'. |
| renaming `$abc$1068$g127' to `_535_'. |
| renaming `$abc$1068$g128' to `_536_'. |
| renaming `$abc$1068$g129' to `_537_'. |
| renaming `$abc$1068$g130' to `_538_'. |
| renaming `$abc$1068$g131' to `_539_'. |
| renaming `$abc$1068$g132' to `_540_'. |
| renaming `$abc$1068$g133' to `_541_'. |
| renaming `$abc$1068$g134' to `_542_'. |
| renaming `$abc$1068$g135' to `_543_'. |
| renaming `$abc$1068$g136' to `_544_'. |
| renaming `$abc$1068$g137' to `_545_'. |
| renaming `$abc$1068$g138' to `_546_'. |
| renaming `$abc$1068$g139' to `_547_'. |
| renaming `$abc$1068$g140' to `_548_'. |
| renaming `$abc$1068$g141' to `_549_'. |
| renaming `$abc$1068$g142' to `_550_'. |
| renaming `$abc$1068$g143' to `_551_'. |
| renaming `$abc$1068$g144' to `_552_'. |
| renaming `$abc$1068$g145' to `_553_'. |
| renaming `$abc$1068$g146' to `_554_'. |
| renaming `$abc$1068$g147' to `_555_'. |
| renaming `$abc$1068$g148' to `_556_'. |
| renaming `$abc$1068$g149' to `_557_'. |
| renaming `$abc$1068$g150' to `_558_'. |
| renaming `$abc$1068$g151' to `_559_'. |
| renaming `$abc$1068$g152' to `_560_'. |
| renaming `$abc$1068$g153' to `_561_'. |
| renaming `$abc$1068$g154' to `_562_'. |
| renaming `$abc$1068$g155' to `_563_'. |
| renaming `$abc$1068$g156' to `_564_'. |
| renaming `$abc$1068$g157' to `_565_'. |
| renaming `$abc$1068$g158' to `_566_'. |
| renaming `$abc$1068$g159' to `_567_'. |
| renaming `$abc$1068$g160' to `_568_'. |
| renaming `$abc$1068$g161' to `_569_'. |
| renaming `$abc$1068$g162' to `_570_'. |
| renaming `$abc$1068$g163' to `_571_'. |
| renaming `$abc$1068$g164' to `_572_'. |
| renaming `$abc$1068$g165' to `_573_'. |
| renaming `$abc$1068$g166' to `_574_'. |
| renaming `$abc$1068$g167' to `_575_'. |
| renaming `$abc$1068$g168' to `_576_'. |
| renaming `$abc$1068$g169' to `_577_'. |
| renaming `$abc$1068$g170' to `_578_'. |
| renaming `$abc$1068$g171' to `_579_'. |
| renaming `$abc$1068$g172' to `_580_'. |
| renaming `$abc$1068$g173' to `_581_'. |
| renaming `$abc$1068$g174' to `_582_'. |
| renaming `$abc$1068$g175' to `_583_'. |
| renaming `$abc$1068$g176' to `_584_'. |
| renaming `$abc$1068$g177' to `_585_'. |
| renaming `$abc$1068$g178' to `_586_'. |
| renaming `$abc$1068$g179' to `_587_'. |
| renaming `$abc$1068$g180' to `_588_'. |
| renaming `$abc$1068$g181' to `_589_'. |
| renaming `$abc$1068$g182' to `_590_'. |
| renaming `$abc$1068$g183' to `_591_'. |
| renaming `$abc$1068$g184' to `_592_'. |
| renaming `$abc$1068$g185' to `_593_'. |
| renaming `$abc$1068$g186' to `_594_'. |
| renaming `$abc$1068$g187' to `_595_'. |
| renaming `$abc$1068$g188' to `_596_'. |
| renaming `$abc$1068$g189' to `_597_'. |
| renaming `$abc$1068$g190' to `_598_'. |
| renaming `$abc$1068$g191' to `_599_'. |
| renaming `$abc$1068$g192' to `_600_'. |
| renaming `$abc$1068$g193' to `_601_'. |
| renaming `$abc$1068$g194' to `_602_'. |
| renaming `$abc$1068$g195' to `_603_'. |
| renaming `$abc$1068$g196' to `_604_'. |
| renaming `$abc$1068$g197' to `_605_'. |
| renaming `$abc$1068$g198' to `_606_'. |
| renaming `$abc$1068$g199' to `_607_'. |
| renaming `$abc$1068$g200' to `_608_'. |
| renaming `$abc$1068$g201' to `_609_'. |
| renaming `$abc$1068$g202' to `_610_'. |
| renaming `$abc$1068$g203' to `_611_'. |
| renaming `$abc$1068$g204' to `_612_'. |
| renaming `$abc$1068$g205' to `_613_'. |
| renaming `$abc$1068$g206' to `_614_'. |
| renaming `$abc$1068$g207' to `_615_'. |
| renaming `$abc$1068$g208' to `_616_'. |
| renaming `$abc$1068$g209' to `_617_'. |
| renaming `$abc$1068$g210' to `_618_'. |
| renaming `$abc$1068$g211' to `_619_'. |
| renaming `$abc$1068$g212' to `_620_'. |
| renaming `$abc$1068$g213' to `_621_'. |
| renaming `$abc$1068$g214' to `_622_'. |
| renaming `$abc$1068$g215' to `_623_'. |
| renaming `$abc$1068$g216' to `_624_'. |
| renaming `$abc$1068$g217' to `_625_'. |
| renaming `$abc$1068$g218' to `_626_'. |
| renaming `$abc$1068$g219' to `_627_'. |
| renaming `$abc$1068$g220' to `_628_'. |
| renaming `$abc$1068$g221' to `_629_'. |
| renaming `$abc$1068$g222' to `_630_'. |
| renaming `$abc$1068$g223' to `_631_'. |
| renaming `$abc$1068$g224' to `_632_'. |
| renaming `$abc$1068$g225' to `_633_'. |
| renaming `$abc$1068$g226' to `_634_'. |
| renaming `$abc$1068$g227' to `_635_'. |
| renaming `$abc$1068$g228' to `_636_'. |
| renaming `$abc$1068$g229' to `_637_'. |
| renaming `$abc$1068$g230' to `_638_'. |
| renaming `$abc$1068$g231' to `_639_'. |
| renaming `$abc$1068$g232' to `_640_'. |
| renaming `$abc$1068$g233' to `_641_'. |
| renaming `$abc$1068$g234' to `_642_'. |
| renaming `$abc$1068$g235' to `_643_'. |
| renaming `$abc$1068$g236' to `_644_'. |
| renaming `$abc$1068$g237' to `_645_'. |
| renaming `$abc$1068$g238' to `_646_'. |
| renaming `$abc$1068$g239' to `_647_'. |
| renaming `$abc$1068$g240' to `_648_'. |
| renaming `$abc$1068$g241' to `_649_'. |
| renaming `$abc$1068$g242' to `_650_'. |
| renaming `$abc$1068$g243' to `_651_'. |
| renaming `$abc$1068$g244' to `_652_'. |
| renaming `$abc$1068$g245' to `_653_'. |
| renaming `$abc$1068$g246' to `_654_'. |
| renaming `$abc$1068$g247' to `_655_'. |
| renaming `$abc$1068$g248' to `_656_'. |
| renaming `$abc$1068$g249' to `_657_'. |
| renaming `$abc$1068$g250' to `_658_'. |
| renaming `$abc$1068$g251' to `_659_'. |
| renaming `$abc$1068$g252' to `_660_'. |
| renaming `$abc$1068$g253' to `_661_'. |
| renaming `$abc$1068$g254' to `_662_'. |
| renaming `$abc$1068$g255' to `_663_'. |
| renaming `$abc$1068$g256' to `_664_'. |
| renaming `$abc$1068$g257' to `_665_'. |
| renaming `$abc$1068$g258' to `_666_'. |
| renaming `$abc$1068$g259' to `_667_'. |
| renaming `$abc$1068$g260' to `_668_'. |
| renaming `$abc$1068$g261' to `_669_'. |
| renaming `$abc$1068$g262' to `_670_'. |
| renaming `$abc$1068$g263' to `_671_'. |
| renaming `$abc$1068$g264' to `_672_'. |
| renaming `$abc$1068$g265' to `_673_'. |
| renaming `$abc$1068$g266' to `_674_'. |
| renaming `$abc$1068$g267' to `_675_'. |
| renaming `$abc$1068$g268' to `_676_'. |
| renaming `$abc$1068$g269' to `_677_'. |
| renaming `$abc$1068$g270' to `_678_'. |
| renaming `$abc$1068$g271' to `_679_'. |
| renaming `$abc$1068$g272' to `_680_'. |
| renaming `$abc$1068$g273' to `_681_'. |
| renaming `$abc$1068$g274' to `_682_'. |
| renaming `$abc$1068$g275' to `_683_'. |
| renaming `$abc$1068$g276' to `_684_'. |
| renaming `$abc$1068$g277' to `_685_'. |
| renaming `$abc$1068$g278' to `_686_'. |
| renaming `$abc$1068$g279' to `_687_'. |
| renaming `$abc$1068$g280' to `_688_'. |
| renaming `$abc$1068$g281' to `_689_'. |
| renaming `$abc$1068$g282' to `_690_'. |
| renaming `$abc$1068$g283' to `_691_'. |
| renaming `$abc$1068$g284' to `_692_'. |
| renaming `$abc$1068$g285' to `_693_'. |
| renaming `$abc$1068$g286' to `_694_'. |
| renaming `$abc$1068$g287' to `_695_'. |
| renaming `$abc$1068$g288' to `_696_'. |
| renaming `$abc$1068$g289' to `_697_'. |
| renaming `$abc$1068$g290' to `_698_'. |
| renaming `$abc$1068$g291' to `_699_'. |
| renaming `$abc$1068$g292' to `_700_'. |
| renaming `$abc$1068$g293' to `_701_'. |
| renaming `$abc$1068$g294' to `_702_'. |
| renaming `$abc$1068$g295' to `_703_'. |
| renaming `$abc$1068$g296' to `_704_'. |
| renaming `$abc$1068$g297' to `_705_'. |
| renaming `$abc$1068$g298' to `_706_'. |
| renaming `$abc$1068$g299' to `_707_'. |
| renaming `$abc$1068$g300' to `_708_'. |
| renaming `$abc$1068$g301' to `_709_'. |
| renaming `$abc$1068$g302' to `_710_'. |
| renaming `$abc$1068$g303' to `_711_'. |
| renaming `$abc$1068$g304' to `_712_'. |
| renaming `$abc$1068$g305' to `_713_'. |
| renaming `$abc$1068$g306' to `_714_'. |
| renaming `$abc$1068$g307' to `_715_'. |
| renaming `$abc$1068$g308' to `_716_'. |
| renaming `$abc$1068$g309' to `_717_'. |
| renaming `$abc$1068$g310' to `_718_'. |
| renaming `$abc$1068$g311' to `_719_'. |
| renaming `$abc$1068$g312' to `_720_'. |
| renaming `$abc$1068$g313' to `_721_'. |
| renaming `$abc$1068$g314' to `_722_'. |
| renaming `$abc$1068$g315' to `_723_'. |
| renaming `$abc$1068$g316' to `_724_'. |
| renaming `$abc$1068$g317' to `_725_'. |
| renaming `$abc$1068$g318' to `_726_'. |
| renaming `$abc$1068$g319' to `_727_'. |
| renaming `$abc$1068$g320' to `_728_'. |
| renaming `$abc$1068$g321' to `_729_'. |
| renaming `$abc$1068$g322' to `_730_'. |
| renaming `$abc$1068$g323' to `_731_'. |
| renaming `$abc$1068$g324' to `_732_'. |
| renaming `$abc$1068$g325' to `_733_'. |
| renaming `$abc$1068$g326' to `_734_'. |
| renaming `$abc$1068$g327' to `_735_'. |
| renaming `$abc$1068$g328' to `_736_'. |
| renaming `$abc$1068$g329' to `_737_'. |
| renaming `$abc$1068$g330' to `_738_'. |
| renaming `$abc$1068$g331' to `_739_'. |
| renaming `$abc$1068$g332' to `_740_'. |
| renaming `$abc$1068$g333' to `_741_'. |
| renaming `$abc$1068$g334' to `_742_'. |
| renaming `$abc$1068$g335' to `_743_'. |
| renaming `$abc$1068$g336' to `_744_'. |
| renaming `$abc$1068$g337' to `_745_'. |
| renaming `$abc$1068$g338' to `_746_'. |
| renaming `$abc$1068$g339' to `_747_'. |
| renaming `$abc$1068$g340' to `_748_'. |
| renaming `$abc$1068$g341' to `_749_'. |
| renaming `$abc$1068$g342' to `_750_'. |
| renaming `$abc$1068$g343' to `_751_'. |
| renaming `$abc$1068$g344' to `_752_'. |
| renaming `$abc$1068$g345' to `_753_'. |
| renaming `$abc$1068$g346' to `_754_'. |
| renaming `$abc$1068$g347' to `_755_'. |
| renaming `$abc$1068$g348' to `_756_'. |
| renaming `$abc$1068$g349' to `_757_'. |
| renaming `$abc$1068$g350' to `_758_'. |
| renaming `$abc$1068$g351' to `_759_'. |
| renaming `$abc$1068$g352' to `_760_'. |
| renaming `$abc$1068$g353' to `_761_'. |
| renaming `$abc$1068$g354' to `_762_'. |
| renaming `$abc$1068$g355' to `_763_'. |
| renaming `$abc$1068$g356' to `_764_'. |
| renaming `$abc$1068$g357' to `_765_'. |
| renaming `$abc$1068$g358' to `_766_'. |
| renaming `$abc$1068$g359' to `_767_'. |
| renaming `$abc$1068$g360' to `_768_'. |
| renaming `$abc$1068$g361' to `_769_'. |
| renaming `$abc$1068$g362' to `_770_'. |
| renaming `$abc$1068$g363' to `_771_'. |
| renaming `$abc$1068$g364' to `_772_'. |
| renaming `$abc$1068$g365' to `_773_'. |
| renaming `$abc$1068$g366' to `_774_'. |
| renaming `$abc$1068$g367' to `_775_'. |
| renaming `$abc$1068$g368' to `_776_'. |
| renaming `$abc$1068$g369' to `_777_'. |
| renaming `$abc$1068$g370' to `_778_'. |
| renaming `$abc$1068$g371' to `_779_'. |
| renaming `$abc$1068$g372' to `_780_'. |
| renaming `$abc$1068$g373' to `_781_'. |
| renaming `$abc$1068$g374' to `_782_'. |
| renaming `$abc$1068$g375' to `_783_'. |
| renaming `$abc$1068$g376' to `_784_'. |
| renaming `$abc$1068$g377' to `_785_'. |
| renaming `$abc$1068$g378' to `_786_'. |
| renaming `$abc$1068$g379' to `_787_'. |
| renaming `$abc$1068$g380' to `_788_'. |
| renaming `$abc$1068$g381' to `_789_'. |
| renaming `$abc$1068$g382' to `_790_'. |
| renaming `$abc$1068$g383' to `_791_'. |
| renaming `$abc$1068$g384' to `_792_'. |
| renaming `$abc$1068$g385' to `_793_'. |
| renaming `$abc$1068$g386' to `_794_'. |
| renaming `$abc$1068$g387' to `_795_'. |
| renaming `$abc$1068$g388' to `_796_'. |
| renaming `$abc$1068$g389' to `_797_'. |
| renaming `$abc$1068$g390' to `_798_'. |
| renaming `$abc$1068$g391' to `_799_'. |
| renaming `$abc$1068$g392' to `_800_'. |
| renaming `$abc$1068$g393' to `_801_'. |
| renaming `$abc$1068$g394' to `_802_'. |
| renaming `$abc$1068$g395' to `_803_'. |
| renaming `$abc$1068$g396' to `_804_'. |
| renaming `$abc$1068$g397' to `_805_'. |
| renaming `$abc$1068$g398' to `_806_'. |
| renaming `$abc$1068$g399' to `_807_'. |
| renaming `$abc$1068$g400' to `_808_'. |
| renaming `$abc$1068$g401' to `_809_'. |
| renaming `$abc$1068$g402' to `_810_'. |
| renaming `$abc$1068$g403' to `_811_'. |
| renaming `$abc$1068$g404' to `_812_'. |
| renaming `$abc$1068$g405' to `_813_'. |
| renaming `$abc$1068$g406' to `_814_'. |
| renaming `$abc$1068$g407' to `_815_'. |
| renaming `$abc$1068$g408' to `_816_'. |
| renaming `$abc$1068$g409' to `_817_'. |
| renaming `$abc$1068$g410' to `_818_'. |
| renaming `$abc$1068$g411' to `_819_'. |
| renaming `$abc$1068$g412' to `_820_'. |
| renaming `$abc$1068$g413' to `_821_'. |
| renaming `$abc$1068$g414' to `_822_'. |
| renaming `$abc$1068$g415' to `_823_'. |
| renaming `$abc$1068$g416' to `_824_'. |
| renaming `$abc$1068$g417' to `_825_'. |
| renaming `$abc$1068$g418' to `_826_'. |
| renaming `$abc$1068$g419' to `_827_'. |
| renaming `$abc$1068$g420' to `_828_'. |
| renaming `$abc$1068$g421' to `_829_'. |
| renaming `$abc$1068$g422' to `_830_'. |
| renaming `$abc$1068$g423' to `_831_'. |
| renaming `$abc$1068$g424' to `_832_'. |
| renaming `$abc$1068$g425' to `_833_'. |
| renaming `$abc$1068$g426' to `_834_'. |
| renaming `$abc$1068$g427' to `_835_'. |
| renaming `$abc$1068$g428' to `_836_'. |
| renaming `$abc$1068$g429' to `_837_'. |
| renaming `$abc$1068$g430' to `_838_'. |
| renaming `$abc$1068$g431' to `_839_'. |
| renaming `$abc$1068$g432' to `_840_'. |
| renaming `$abc$1068$g433' to `_841_'. |
| renaming `$abc$1068$g434' to `_842_'. |
| renaming `$abc$1068$g435' to `_843_'. |
| renaming `$abc$1068$g436' to `_844_'. |
| renaming `$abc$1068$g437' to `_845_'. |
| renaming `$abc$1068$g438' to `_846_'. |
| renaming `$abc$1068$n121_1' to `_017_'. |
| renaming `$abc$1068$n122' to `_018_'. |
| renaming `$abc$1068$n123_1' to `_019_'. |
| renaming `$abc$1068$n124_1' to `_020_'. |
| renaming `$abc$1068$n125' to `_021_'. |
| renaming `$abc$1068$n126_1' to `_022_'. |
| renaming `$abc$1068$n127_1' to `_023_'. |
| renaming `$abc$1068$n128' to `_024_'. |
| renaming `$abc$1068$n129_1' to `_025_'. |
| renaming `$abc$1068$n130_1' to `_026_'. |
| renaming `$abc$1068$n131' to `_027_'. |
| renaming `$abc$1068$n132_1' to `_028_'. |
| renaming `$abc$1068$n133_1' to `_029_'. |
| renaming `$abc$1068$n134' to `_030_'. |
| renaming `$abc$1068$n135_1' to `_031_'. |
| renaming `$abc$1068$n136_1' to `_032_'. |
| renaming `$abc$1068$n137' to `_033_'. |
| renaming `$abc$1068$n138' to `_034_'. |
| renaming `$abc$1068$n139' to `_035_'. |
| renaming `$abc$1068$n140' to `_036_'. |
| renaming `$abc$1068$n141' to `_037_'. |
| renaming `$abc$1068$n142' to `_038_'. |
| renaming `$abc$1068$n143' to `_039_'. |
| renaming `$abc$1068$n144' to `_040_'. |
| renaming `$abc$1068$n145' to `_041_'. |
| renaming `$abc$1068$n146' to `_042_'. |
| renaming `$abc$1068$n147' to `_043_'. |
| renaming `$abc$1068$n148' to `_044_'. |
| renaming `$abc$1068$n149' to `_045_'. |
| renaming `$abc$1068$n150' to `_046_'. |
| renaming `$abc$1068$n151' to `_047_'. |
| renaming `$abc$1068$n152' to `_048_'. |
| renaming `$abc$1068$n153' to `_049_'. |
| renaming `$abc$1068$n154' to `_050_'. |
| renaming `$abc$1068$n155' to `_051_'. |
| renaming `$abc$1068$n156' to `_052_'. |
| renaming `$abc$1068$n157' to `_053_'. |
| renaming `$abc$1068$n158' to `_054_'. |
| renaming `$abc$1068$n160' to `_055_'. |
| renaming `$abc$1068$n161' to `_056_'. |
| renaming `$abc$1068$n163' to `_057_'. |
| renaming `$abc$1068$n164' to `_058_'. |
| renaming `$abc$1068$n165' to `_059_'. |
| renaming `$abc$1068$n166' to `_060_'. |
| renaming `$abc$1068$n167' to `_061_'. |
| renaming `$abc$1068$n168' to `_062_'. |
| renaming `$abc$1068$n169' to `_063_'. |
| renaming `$abc$1068$n170' to `_064_'. |
| renaming `$abc$1068$n171_1' to `_065_'. |
| renaming `$abc$1068$n172_1' to `_066_'. |
| renaming `$abc$1068$n174_1' to `_067_'. |
| renaming `$abc$1068$n175_1' to `_068_'. |
| renaming `$abc$1068$n176_1' to `_069_'. |
| renaming `$abc$1068$n177_1' to `_070_'. |
| renaming `$abc$1068$n179_1' to `_071_'. |
| renaming `$abc$1068$n180_1' to `_072_'. |
| renaming `$abc$1068$n181_1' to `_073_'. |
| renaming `$abc$1068$n182_1' to `_074_'. |
| renaming `$abc$1068$n184_1' to `_075_'. |
| renaming `$abc$1068$n185_1' to `_076_'. |
| renaming `$abc$1068$n186_1' to `_077_'. |
| renaming `$abc$1068$n187' to `_078_'. |
| renaming `$abc$1068$n189_1' to `_079_'. |
| renaming `$abc$1068$n190_1' to `_080_'. |
| renaming `$abc$1068$n191_1' to `_081_'. |
| renaming `$abc$1068$n192_1' to `_082_'. |
| renaming `$abc$1068$n194_1' to `_083_'. |
| renaming `$abc$1068$n195_1' to `_084_'. |
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| renaming `$procdff$881.V[0].P.PN.PN0.ff' to `_875_'. |
| renaming `$procdff$881.V[10].P.PN.PN0.ff' to `_876_'. |
| renaming `$procdff$881.V[11].P.PN.PN0.ff' to `_877_'. |
| renaming `$procdff$881.V[12].P.PN.PN0.ff' to `_878_'. |
| renaming `$procdff$881.V[13].P.PN.PN0.ff' to `_879_'. |
| renaming `$procdff$881.V[14].P.PN.PN0.ff' to `_880_'. |
| renaming `$procdff$881.V[15].P.PN.PN0.ff' to `_881_'. |
| renaming `$procdff$881.V[16].P.PN.PN0.ff' to `_882_'. |
| renaming `$procdff$881.V[1].P.PN.PN0.ff' to `_883_'. |
| renaming `$procdff$881.V[2].P.PN.PN0.ff' to `_884_'. |
| renaming `$procdff$881.V[3].P.PN.PN0.ff' to `_885_'. |
| renaming `$procdff$881.V[4].P.PN.PN0.ff' to `_886_'. |
| renaming `$procdff$881.V[5].P.PN.PN0.ff' to `_887_'. |
| renaming `$procdff$881.V[6].P.PN.PN0.ff' to `_888_'. |
| renaming `$procdff$881.V[7].P.PN.PN0.ff' to `_889_'. |
| renaming `$procdff$881.V[8].P.PN.PN0.ff' to `_890_'. |
| renaming `$procdff$881.V[9].P.PN.PN0.ff' to `_891_'. |
| renaming `$procdff$882.V[0].P.PN.PN0.ff' to `_892_'. |
| renaming `$procdff$883.V[0].P.PN.PN1.ff' to `_893_'. |
| renaming `$procdff$884.V[0].P.PN.PN0.ff' to `_894_'. |
| renaming `$procdff$885.V[0].P.PN.PN1.ff' to `_895_'. |
| Dumping module `\i2c_master_byte_ctrl'. |
| renaming `$0\ack_out[0:0]' to `_000_'. |
| renaming `$0\c_state[4:0]' to `_001_'. |
| renaming `$0\cmd_ack[0:0]' to `_002_'. |
| renaming `$0\core_cmd[3:0]' to `_003_'. |
| renaming `$0\core_txd[0:0]' to `_004_'. |
| renaming `$0\dcnt[2:0]' to `_005_'. |
| renaming `$0\ld[0:0]' to `_006_'. |
| renaming `$0\shift[0:0]' to `_007_'. |
| renaming `$0\sr[7:0]' to `_008_'. |
| renaming `$abc$1069$g000' to `_205_'. |
| renaming `$abc$1069$g001' to `_206_'. |
| renaming `$abc$1069$g002' to `_207_'. |
| renaming `$abc$1069$g003' to `_208_'. |
| renaming `$abc$1069$g004' to `_209_'. |
| renaming `$abc$1069$g005' to `_210_'. |
| renaming `$abc$1069$g006' to `_211_'. |
| renaming `$abc$1069$g007' to `_212_'. |
| renaming `$abc$1069$g008' to `_213_'. |
| renaming `$abc$1069$g009' to `_214_'. |
| renaming `$abc$1069$g010' to `_215_'. |
| renaming `$abc$1069$g011' to `_216_'. |
| renaming `$abc$1069$g012' to `_217_'. |
| renaming `$abc$1069$g013' to `_218_'. |
| renaming `$abc$1069$g014' to `_219_'. |
| renaming `$abc$1069$g015' to `_220_'. |
| renaming `$abc$1069$g016' to `_221_'. |
| renaming `$abc$1069$g017' to `_222_'. |
| renaming `$abc$1069$g018' to `_223_'. |
| renaming `$abc$1069$g019' to `_224_'. |
| renaming `$abc$1069$g020' to `_225_'. |
| renaming `$abc$1069$g021' to `_226_'. |
| renaming `$abc$1069$g022' to `_227_'. |
| renaming `$abc$1069$g023' to `_228_'. |
| renaming `$abc$1069$g024' to `_229_'. |
| renaming `$abc$1069$g025' to `_230_'. |
| renaming `$abc$1069$g026' to `_231_'. |
| renaming `$abc$1069$g027' to `_232_'. |
| renaming `$abc$1069$g028' to `_233_'. |
| renaming `$abc$1069$g029' to `_234_'. |
| renaming `$abc$1069$g030' to `_235_'. |
| renaming `$abc$1069$g031' to `_236_'. |
| renaming `$abc$1069$g032' to `_237_'. |
| renaming `$abc$1069$g033' to `_238_'. |
| renaming `$abc$1069$g034' to `_239_'. |
| renaming `$abc$1069$g035' to `_240_'. |
| renaming `$abc$1069$g036' to `_241_'. |
| renaming `$abc$1069$g037' to `_242_'. |
| renaming `$abc$1069$g038' to `_243_'. |
| renaming `$abc$1069$g039' to `_244_'. |
| renaming `$abc$1069$g040' to `_245_'. |
| renaming `$abc$1069$g041' to `_246_'. |
| renaming `$abc$1069$g042' to `_247_'. |
| renaming `$abc$1069$g043' to `_248_'. |
| renaming `$abc$1069$g044' to `_249_'. |
| renaming `$abc$1069$g045' to `_250_'. |
| renaming `$abc$1069$g046' to `_251_'. |
| renaming `$abc$1069$g047' to `_252_'. |
| renaming `$abc$1069$g048' to `_253_'. |
| renaming `$abc$1069$g049' to `_254_'. |
| renaming `$abc$1069$g050' to `_255_'. |
| renaming `$abc$1069$g051' to `_256_'. |
| renaming `$abc$1069$g052' to `_257_'. |
| renaming `$abc$1069$g053' to `_258_'. |
| renaming `$abc$1069$g054' to `_259_'. |
| renaming `$abc$1069$g055' to `_260_'. |
| renaming `$abc$1069$g056' to `_261_'. |
| renaming `$abc$1069$g057' to `_262_'. |
| renaming `$abc$1069$g058' to `_263_'. |
| renaming `$abc$1069$g059' to `_264_'. |
| renaming `$abc$1069$g060' to `_265_'. |
| renaming `$abc$1069$g061' to `_266_'. |
| renaming `$abc$1069$g062' to `_267_'. |
| renaming `$abc$1069$g063' to `_268_'. |
| renaming `$abc$1069$g064' to `_269_'. |
| renaming `$abc$1069$g065' to `_270_'. |
| renaming `$abc$1069$g066' to `_271_'. |
| renaming `$abc$1069$g067' to `_272_'. |
| renaming `$abc$1069$g068' to `_273_'. |
| renaming `$abc$1069$g069' to `_274_'. |
| renaming `$abc$1069$g070' to `_275_'. |
| renaming `$abc$1069$g071' to `_276_'. |
| renaming `$abc$1069$g072' to `_277_'. |
| renaming `$abc$1069$g073' to `_278_'. |
| renaming `$abc$1069$g074' to `_279_'. |
| renaming `$abc$1069$g075' to `_280_'. |
| renaming `$abc$1069$g076' to `_281_'. |
| renaming `$abc$1069$g077' to `_282_'. |
| renaming `$abc$1069$g078' to `_283_'. |
| renaming `$abc$1069$g079' to `_284_'. |
| renaming `$abc$1069$g080' to `_285_'. |
| renaming `$abc$1069$g081' to `_286_'. |
| renaming `$abc$1069$g082' to `_287_'. |
| renaming `$abc$1069$g083' to `_288_'. |
| renaming `$abc$1069$g084' to `_289_'. |
| renaming `$abc$1069$g085' to `_290_'. |
| renaming `$abc$1069$g086' to `_291_'. |
| renaming `$abc$1069$g087' to `_292_'. |
| renaming `$abc$1069$g088' to `_293_'. |
| renaming `$abc$1069$g089' to `_294_'. |
| renaming `$abc$1069$g090' to `_295_'. |
| renaming `$abc$1069$g091' to `_296_'. |
| renaming `$abc$1069$g092' to `_297_'. |
| renaming `$abc$1069$g093' to `_298_'. |
| renaming `$abc$1069$g094' to `_299_'. |
| renaming `$abc$1069$g095' to `_300_'. |
| renaming `$abc$1069$g096' to `_301_'. |
| renaming `$abc$1069$g097' to `_302_'. |
| renaming `$abc$1069$g098' to `_303_'. |
| renaming `$abc$1069$g099' to `_304_'. |
| renaming `$abc$1069$g100' to `_305_'. |
| renaming `$abc$1069$g101' to `_306_'. |
| renaming `$abc$1069$g102' to `_307_'. |
| renaming `$abc$1069$g103' to `_308_'. |
| renaming `$abc$1069$g104' to `_309_'. |
| renaming `$abc$1069$g105' to `_310_'. |
| renaming `$abc$1069$g106' to `_311_'. |
| renaming `$abc$1069$g107' to `_312_'. |
| renaming `$abc$1069$g108' to `_313_'. |
| renaming `$abc$1069$g109' to `_314_'. |
| renaming `$abc$1069$g110' to `_315_'. |
| renaming `$abc$1069$g111' to `_316_'. |
| renaming `$abc$1069$g112' to `_317_'. |
| renaming `$abc$1069$g113' to `_318_'. |
| renaming `$abc$1069$g114' to `_319_'. |
| renaming `$abc$1069$g115' to `_320_'. |
| renaming `$abc$1069$g116' to `_321_'. |
| renaming `$abc$1069$g117' to `_322_'. |
| renaming `$abc$1069$g118' to `_323_'. |
| renaming `$abc$1069$g119' to `_324_'. |
| renaming `$abc$1069$g120' to `_325_'. |
| renaming `$abc$1069$g121' to `_326_'. |
| renaming `$abc$1069$g122' to `_327_'. |
| renaming `$abc$1069$g123' to `_328_'. |
| renaming `$abc$1069$g124' to `_329_'. |
| renaming `$abc$1069$g125' to `_330_'. |
| renaming `$abc$1069$g126' to `_331_'. |
| renaming `$abc$1069$g127' to `_332_'. |
| renaming `$abc$1069$g128' to `_333_'. |
| renaming `$abc$1069$g129' to `_334_'. |
| renaming `$abc$1069$g130' to `_335_'. |
| renaming `$abc$1069$g131' to `_336_'. |
| renaming `$abc$1069$g132' to `_337_'. |
| renaming `$abc$1069$g133' to `_338_'. |
| renaming `$abc$1069$g134' to `_339_'. |
| renaming `$abc$1069$g135' to `_340_'. |
| renaming `$abc$1069$g136' to `_341_'. |
| renaming `$abc$1069$g137' to `_342_'. |
| renaming `$abc$1069$g138' to `_343_'. |
| renaming `$abc$1069$g139' to `_344_'. |
| renaming `$abc$1069$g140' to `_345_'. |
| renaming `$abc$1069$g141' to `_346_'. |
| renaming `$abc$1069$g142' to `_347_'. |
| renaming `$abc$1069$g143' to `_348_'. |
| renaming `$abc$1069$g144' to `_349_'. |
| renaming `$abc$1069$g145' to `_350_'. |
| renaming `$abc$1069$g146' to `_351_'. |
| renaming `$abc$1069$g147' to `_352_'. |
| renaming `$abc$1069$g148' to `_353_'. |
| renaming `$abc$1069$g149' to `_354_'. |
| renaming `$abc$1069$g150' to `_355_'. |
| renaming `$abc$1069$g151' to `_356_'. |
| renaming `$abc$1069$g152' to `_357_'. |
| renaming `$abc$1069$g153' to `_358_'. |
| renaming `$abc$1069$g154' to `_359_'. |
| renaming `$abc$1069$g155' to `_360_'. |
| renaming `$abc$1069$g156' to `_361_'. |
| renaming `$abc$1069$g157' to `_362_'. |
| renaming `$abc$1069$g158' to `_363_'. |
| renaming `$abc$1069$g159' to `_364_'. |
| renaming `$abc$1069$g160' to `_365_'. |
| renaming `$abc$1069$g161' to `_366_'. |
| renaming `$abc$1069$g162' to `_367_'. |
| renaming `$abc$1069$g163' to `_368_'. |
| renaming `$abc$1069$g164' to `_369_'. |
| renaming `$abc$1069$g165' to `_370_'. |
| renaming `$abc$1069$g166' to `_371_'. |
| renaming `$abc$1069$g167' to `_372_'. |
| renaming `$abc$1069$g168' to `_373_'. |
| renaming `$abc$1069$g169' to `_374_'. |
| renaming `$abc$1069$g170' to `_375_'. |
| renaming `$abc$1069$g171' to `_376_'. |
| renaming `$abc$1069$g172' to `_377_'. |
| renaming `$abc$1069$g173' to `_378_'. |
| renaming `$abc$1069$g174' to `_379_'. |
| renaming `$abc$1069$g175' to `_380_'. |
| renaming `$abc$1069$g176' to `_381_'. |
| renaming `$abc$1069$g177' to `_382_'. |
| renaming `$abc$1069$g178' to `_383_'. |
| renaming `$abc$1069$g179' to `_384_'. |
| renaming `$abc$1069$g180' to `_385_'. |
| renaming `$abc$1069$g181' to `_386_'. |
| renaming `$abc$1069$g182' to `_387_'. |
| renaming `$abc$1069$g183' to `_388_'. |
| renaming `$abc$1069$g184' to `_389_'. |
| renaming `$abc$1069$g185' to `_390_'. |
| renaming `$abc$1069$g186' to `_391_'. |
| renaming `$abc$1069$g187' to `_392_'. |
| renaming `$abc$1069$g188' to `_393_'. |
| renaming `$abc$1069$g189' to `_394_'. |
| renaming `$abc$1069$g190' to `_395_'. |
| renaming `$abc$1069$g191' to `_396_'. |
| renaming `$abc$1069$g192' to `_397_'. |
| renaming `$abc$1069$g193' to `_398_'. |
| renaming `$abc$1069$g194' to `_399_'. |
| renaming `$abc$1069$g195' to `_400_'. |
| renaming `$abc$1069$g196' to `_401_'. |
| renaming `$abc$1069$g197' to `_402_'. |
| renaming `$abc$1069$g198' to `_403_'. |
| renaming `$abc$1069$g199' to `_404_'. |
| renaming `$abc$1069$g200' to `_405_'. |
| renaming `$abc$1069$g201' to `_406_'. |
| renaming `$abc$1069$g202' to `_407_'. |
| renaming `$abc$1069$g203' to `_408_'. |
| renaming `$abc$1069$g204' to `_409_'. |
| renaming `$abc$1069$g205' to `_410_'. |
| renaming `$abc$1069$g206' to `_411_'. |
| renaming `$abc$1069$g207' to `_412_'. |
| renaming `$abc$1069$g208' to `_413_'. |
| renaming `$abc$1069$g209' to `_414_'. |
| renaming `$abc$1069$g210' to `_415_'. |
| renaming `$abc$1069$g211' to `_416_'. |
| renaming `$abc$1069$g212' to `_417_'. |
| renaming `$abc$1069$g213' to `_418_'. |
| renaming `$abc$1069$g214' to `_419_'. |
| renaming `$abc$1069$g215' to `_420_'. |
| renaming `$abc$1069$g216' to `_421_'. |
| renaming `$abc$1069$g217' to `_422_'. |
| renaming `$abc$1069$g218' to `_423_'. |
| renaming `$abc$1069$g219' to `_424_'. |
| renaming `$abc$1069$g220' to `_425_'. |
| renaming `$abc$1069$n100' to `_009_'. |
| renaming `$abc$1069$n101' to `_010_'. |
| renaming `$abc$1069$n102' to `_011_'. |
| renaming `$abc$1069$n103' to `_012_'. |
| renaming `$abc$1069$n104' to `_013_'. |
| renaming `$abc$1069$n106' to `_014_'. |
| renaming `$abc$1069$n107' to `_015_'. |
| renaming `$abc$1069$n108' to `_016_'. |
| renaming `$abc$1069$n109' to `_017_'. |
| renaming `$abc$1069$n110' to `_018_'. |
| renaming `$abc$1069$n111_1' to `_019_'. |
| renaming `$abc$1069$n112' to `_020_'. |
| renaming `$abc$1069$n113' to `_021_'. |
| renaming `$abc$1069$n114' to `_022_'. |
| renaming `$abc$1069$n115' to `_023_'. |
| renaming `$abc$1069$n116' to `_024_'. |
| renaming `$abc$1069$n117' to `_025_'. |
| renaming `$abc$1069$n119' to `_026_'. |
| renaming `$abc$1069$n120' to `_027_'. |
| renaming `$abc$1069$n121' to `_028_'. |
| renaming `$abc$1069$n122_1' to `_029_'. |
| renaming `$abc$1069$n123' to `_030_'. |
| renaming `$abc$1069$n124_1' to `_031_'. |
| renaming `$abc$1069$n125' to `_032_'. |
| renaming `$abc$1069$n126_1' to `_033_'. |
| renaming `$abc$1069$n127' to `_034_'. |
| renaming `$abc$1069$n128_1' to `_035_'. |
| renaming `$abc$1069$n129' to `_036_'. |
| renaming `$abc$1069$n130_1' to `_037_'. |
| renaming `$abc$1069$n131' to `_038_'. |
| renaming `$abc$1069$n132' to `_039_'. |
| renaming `$abc$1069$n133' to `_040_'. |
| renaming `$abc$1069$n134' to `_041_'. |
| renaming `$abc$1069$n135_1' to `_042_'. |
| renaming `$abc$1069$n136_1' to `_043_'. |
| renaming `$abc$1069$n137' to `_044_'. |
| renaming `$abc$1069$n138_1' to `_045_'. |
| renaming `$abc$1069$n139' to `_046_'. |
| renaming `$abc$1069$n140_1' to `_047_'. |
| renaming `$abc$1069$n141' to `_048_'. |
| renaming `$abc$1069$n142_1' to `_049_'. |
| renaming `$abc$1069$n143' to `_050_'. |
| renaming `$abc$1069$n144' to `_051_'. |
| renaming `$abc$1069$n145' to `_052_'. |
| renaming `$abc$1069$n146' to `_053_'. |
| renaming `$abc$1069$n147' to `_054_'. |
| renaming `$abc$1069$n148' to `_055_'. |
| renaming `$abc$1069$n149' to `_056_'. |
| renaming `$abc$1069$n156_1' to `_057_'. |
| renaming `$abc$1069$n157' to `_058_'. |
| renaming `$abc$1069$n159' to `_059_'. |
| renaming `$abc$1069$n160_1' to `_060_'. |
| renaming `$abc$1069$n161' to `_061_'. |
| renaming `$abc$1069$n162_1' to `_062_'. |
| renaming `$abc$1069$n163_1' to `_063_'. |
| renaming `$abc$1069$n165' to `_064_'. |
| renaming `$abc$1069$n166' to `_065_'. |
| renaming `$abc$1069$n167_1' to `_066_'. |
| renaming `$abc$1069$n169' to `_067_'. |
| renaming `$abc$1069$n170_1' to `_068_'. |
| renaming `$abc$1069$n174' to `_069_'. |
| renaming `$abc$1069$n175' to `_070_'. |
| renaming `$abc$1069$n176' to `_071_'. |
| renaming `$abc$1069$n178' to `_072_'. |
| renaming `$abc$1069$n179' to `_073_'. |
| renaming `$abc$1069$n180' to `_074_'. |
| renaming `$abc$1069$n181' to `_075_'. |
| renaming `$abc$1069$n182' to `_076_'. |
| renaming `$abc$1069$n183' to `_077_'. |
| renaming `$abc$1069$n184' to `_078_'. |
| renaming `$abc$1069$n185' to `_079_'. |
| renaming `$abc$1069$n187' to `_080_'. |
| renaming `$abc$1069$n188' to `_081_'. |
| renaming `$abc$1069$n192' to `_082_'. |
| renaming `$abc$1069$n193' to `_083_'. |
| renaming `$abc$1069$n194' to `_084_'. |
| renaming `$abc$1069$n196' to `_085_'. |
| renaming `$abc$1069$n200' to `_086_'. |
| renaming `$abc$1069$n203' to `_087_'. |
| renaming `$abc$1069$n204' to `_088_'. |
| renaming `$abc$1069$n205' to `_089_'. |
| renaming `$abc$1069$n206' to `_090_'. |
| renaming `$abc$1069$n207' to `_091_'. |
| renaming `$abc$1069$n208' to `_092_'. |
| renaming `$abc$1069$n209' to `_093_'. |
| renaming `$abc$1069$n211' to `_094_'. |
| renaming `$abc$1069$n212' to `_095_'. |
| renaming `$abc$1069$n213' to `_096_'. |
| renaming `$abc$1069$n214' to `_097_'. |
| renaming `$abc$1069$n219' to `_098_'. |
| renaming `$abc$1069$n220' to `_099_'. |
| renaming `$abc$1069$n223' to `_100_'. |
| renaming `$abc$1069$n224' to `_101_'. |
| renaming `$abc$1069$n226' to `_102_'. |
| renaming `$abc$1069$n227' to `_103_'. |
| renaming `$abc$1069$n228' to `_104_'. |
| renaming `$abc$1069$n229' to `_105_'. |
| renaming `$abc$1069$n230' to `_106_'. |
| renaming `$abc$1069$n231' to `_107_'. |
| renaming `$abc$1069$n232' to `_108_'. |
| renaming `$abc$1069$n234' to `_109_'. |
| renaming `$abc$1069$n235' to `_110_'. |
| renaming `$abc$1069$n236' to `_111_'. |
| renaming `$abc$1069$n237' to `_112_'. |
| renaming `$abc$1069$n238' to `_113_'. |
| renaming `$abc$1069$n239' to `_114_'. |
| renaming `$abc$1069$n240' to `_115_'. |
| renaming `$abc$1069$n241' to `_116_'. |
| renaming `$abc$1069$n242' to `_117_'. |
| renaming `$abc$1069$n243' to `_118_'. |
| renaming `$abc$1069$n244' to `_119_'. |
| renaming `$abc$1069$n245' to `_120_'. |
| renaming `$abc$1069$n247' to `_121_'. |
| renaming `$abc$1069$n248' to `_122_'. |
| renaming `$abc$1069$n249' to `_123_'. |
| renaming `$abc$1069$n250' to `_124_'. |
| renaming `$abc$1069$n251' to `_125_'. |
| renaming `$abc$1069$n252' to `_126_'. |
| renaming `$abc$1069$n253' to `_127_'. |
| renaming `$abc$1069$n254' to `_128_'. |
| renaming `$abc$1069$n255' to `_129_'. |
| renaming `$abc$1069$n256' to `_130_'. |
| renaming `$abc$1069$n257' to `_131_'. |
| renaming `$abc$1069$n258' to `_132_'. |
| renaming `$abc$1069$n259' to `_133_'. |
| renaming `$abc$1069$n261' to `_134_'. |
| renaming `$abc$1069$n262' to `_135_'. |
| renaming `$abc$1069$n263' to `_136_'. |
| renaming `$abc$1069$n264' to `_137_'. |
| renaming `$abc$1069$n265' to `_138_'. |
| renaming `$abc$1069$n266' to `_139_'. |
| renaming `$abc$1069$n267' to `_140_'. |
| renaming `$abc$1069$n268' to `_141_'. |
| renaming `$abc$1069$n269' to `_142_'. |
| renaming `$abc$1069$n270' to `_143_'. |
| renaming `$abc$1069$n271' to `_144_'. |
| renaming `$abc$1069$n272' to `_145_'. |
| renaming `$abc$1069$n273' to `_146_'. |
| renaming `$abc$1069$n274' to `_147_'. |
| renaming `$abc$1069$n275' to `_148_'. |
| renaming `$abc$1069$n277' to `_149_'. |
| renaming `$abc$1069$n278' to `_150_'. |
| renaming `$abc$1069$n279' to `_151_'. |
| renaming `$abc$1069$n280' to `_152_'. |
| renaming `$abc$1069$n281' to `_153_'. |
| renaming `$abc$1069$n282' to `_154_'. |
| renaming `$abc$1069$n283' to `_155_'. |
| renaming `$abc$1069$n284' to `_156_'. |
| renaming `$abc$1069$n285' to `_157_'. |
| renaming `$abc$1069$n286' to `_158_'. |
| renaming `$abc$1069$n287' to `_159_'. |
| renaming `$abc$1069$n288' to `_160_'. |
| renaming `$abc$1069$n289' to `_161_'. |
| renaming `$abc$1069$n290' to `_162_'. |
| renaming `$abc$1069$n291' to `_163_'. |
| renaming `$abc$1069$n293' to `_164_'. |
| renaming `$abc$1069$n294' to `_165_'. |
| renaming `$abc$1069$n295' to `_166_'. |
| renaming `$abc$1069$n296' to `_167_'. |
| renaming `$abc$1069$n297' to `_168_'. |
| renaming `$abc$1069$n298' to `_169_'. |
| renaming `$abc$1069$n300' to `_170_'. |
| renaming `$abc$1069$n301' to `_171_'. |
| renaming `$abc$1069$n302' to `_172_'. |
| renaming `$abc$1069$n303' to `_173_'. |
| renaming `$abc$1069$n304' to `_174_'. |
| renaming `$abc$1069$n305' to `_175_'. |
| renaming `$abc$1069$n307' to `_176_'. |
| renaming `$abc$1069$n308' to `_177_'. |
| renaming `$abc$1069$n309' to `_178_'. |
| renaming `$abc$1069$n310' to `_179_'. |
| renaming `$abc$1069$n311' to `_180_'. |
| renaming `$abc$1069$n66' to `_181_'. |
| renaming `$abc$1069$n67' to `_182_'. |
| renaming `$abc$1069$n68_1' to `_183_'. |
| renaming `$abc$1069$n70' to `_184_'. |
| renaming `$abc$1069$n71_1' to `_185_'. |
| renaming `$abc$1069$n73' to `_186_'. |
| renaming `$abc$1069$n74' to `_187_'. |
| renaming `$abc$1069$n76' to `_188_'. |
| renaming `$abc$1069$n77_1' to `_189_'. |
| renaming `$abc$1069$n79_1' to `_190_'. |
| renaming `$abc$1069$n80_1' to `_191_'. |
| renaming `$abc$1069$n82' to `_192_'. |
| renaming `$abc$1069$n83' to `_193_'. |
| renaming `$abc$1069$n85_1' to `_194_'. |
| renaming `$abc$1069$n86_1' to `_195_'. |
| renaming `$abc$1069$n88_1' to `_196_'. |
| renaming `$abc$1069$n89' to `_197_'. |
| renaming `$abc$1069$n91' to `_198_'. |
| renaming `$abc$1069$n92_1' to `_199_'. |
| renaming `$abc$1069$n94_1' to `_200_'. |
| renaming `$abc$1069$n95' to `_201_'. |
| renaming `$abc$1069$n96' to `_202_'. |
| renaming `$abc$1069$n97' to `_203_'. |
| renaming `$abc$1069$n98' to `_204_'. |
| renaming `$procdff$886.V[0].P.PN.PN0.ff' to `_426_'. |
| renaming `$procdff$886.V[1].P.PN.PN0.ff' to `_427_'. |
| renaming `$procdff$886.V[2].P.PN.PN0.ff' to `_428_'. |
| renaming `$procdff$886.V[3].P.PN.PN0.ff' to `_429_'. |
| renaming `$procdff$886.V[4].P.PN.PN0.ff' to `_430_'. |
| renaming `$procdff$886.V[5].P.PN.PN0.ff' to `_431_'. |
| renaming `$procdff$886.V[6].P.PN.PN0.ff' to `_432_'. |
| renaming `$procdff$886.V[7].P.PN.PN0.ff' to `_433_'. |
| renaming `$procdff$887.V[0].P.PN.PN0.ff' to `_434_'. |
| renaming `$procdff$887.V[1].P.PN.PN0.ff' to `_435_'. |
| renaming `$procdff$887.V[2].P.PN.PN0.ff' to `_436_'. |
| renaming `$procdff$888.V[0].P.PN.PN0.ff' to `_437_'. |
| renaming `$procdff$889.V[0].P.PN.PN0.ff' to `_438_'. |
| renaming `$procdff$889.V[1].P.PN.PN0.ff' to `_439_'. |
| renaming `$procdff$889.V[2].P.PN.PN0.ff' to `_440_'. |
| renaming `$procdff$889.V[3].P.PN.PN0.ff' to `_441_'. |
| renaming `$procdff$889.V[4].P.PN.PN0.ff' to `_442_'. |
| renaming `$procdff$890.V[0].P.PN.PN0.ff' to `_443_'. |
| renaming `$procdff$891.V[0].P.PN.PN0.ff' to `_444_'. |
| renaming `$procdff$891.V[1].P.PN.PN0.ff' to `_445_'. |
| renaming `$procdff$891.V[2].P.PN.PN0.ff' to `_446_'. |
| renaming `$procdff$891.V[3].P.PN.PN0.ff' to `_447_'. |
| renaming `$procdff$892.V[0].P.PN.PN0.ff' to `_448_'. |
| renaming `$procdff$893.V[0].P.PN.PN0.ff' to `_449_'. |
| renaming `$procdff$894.V[0].P.PN.PN0.ff' to `_450_'. |
| Dumping module `\i2c_master_top'. |
| renaming `$0\al[0:0]' to `_000_'. |
| renaming `$0\cr[7:0]' to `_001_'. |
| renaming `$0\ctr[7:0]' to `_002_'. |
| renaming `$0\irq_flag[0:0]' to `_003_'. |
| renaming `$0\prer[15:0]' to `_004_'. |
| renaming `$0\rxack[0:0]' to `_005_'. |
| renaming `$0\tip[0:0]' to `_006_'. |
| renaming `$0\txr[7:0]' to `_007_'. |
| renaming `$0\wb_ack_o[0:0]' to `_008_'. |
| renaming `$0\wb_dat_o[7:0]' to `_009_'. |
| renaming `$0\wb_inta_o[0:0]' to `_010_'. |
| renaming `$abc$1070$g000' to `_227_'. |
| renaming `$abc$1070$g001' to `_228_'. |
| renaming `$abc$1070$g002' to `_229_'. |
| renaming `$abc$1070$g003' to `_230_'. |
| renaming `$abc$1070$g004' to `_231_'. |
| renaming `$abc$1070$g005' to `_232_'. |
| renaming `$abc$1070$g006' to `_233_'. |
| renaming `$abc$1070$g007' to `_234_'. |
| renaming `$abc$1070$g008' to `_235_'. |
| renaming `$abc$1070$g009' to `_236_'. |
| renaming `$abc$1070$g010' to `_237_'. |
| renaming `$abc$1070$g011' to `_238_'. |
| renaming `$abc$1070$g012' to `_239_'. |
| renaming `$abc$1070$g013' to `_240_'. |
| renaming `$abc$1070$g014' to `_241_'. |
| renaming `$abc$1070$g015' to `_242_'. |
| renaming `$abc$1070$g016' to `_243_'. |
| renaming `$abc$1070$g017' to `_244_'. |
| renaming `$abc$1070$g018' to `_245_'. |
| renaming `$abc$1070$g019' to `_246_'. |
| renaming `$abc$1070$g020' to `_247_'. |
| renaming `$abc$1070$g021' to `_248_'. |
| renaming `$abc$1070$g022' to `_249_'. |
| renaming `$abc$1070$g023' to `_250_'. |
| renaming `$abc$1070$g024' to `_251_'. |
| renaming `$abc$1070$g025' to `_252_'. |
| renaming `$abc$1070$g026' to `_253_'. |
| renaming `$abc$1070$g027' to `_254_'. |
| renaming `$abc$1070$g028' to `_255_'. |
| renaming `$abc$1070$g029' to `_256_'. |
| renaming `$abc$1070$g030' to `_257_'. |
| renaming `$abc$1070$g031' to `_258_'. |
| renaming `$abc$1070$g032' to `_259_'. |
| renaming `$abc$1070$g033' to `_260_'. |
| renaming `$abc$1070$g034' to `_261_'. |
| renaming `$abc$1070$g035' to `_262_'. |
| renaming `$abc$1070$g036' to `_263_'. |
| renaming `$abc$1070$g037' to `_264_'. |
| renaming `$abc$1070$g038' to `_265_'. |
| renaming `$abc$1070$g039' to `_266_'. |
| renaming `$abc$1070$g040' to `_267_'. |
| renaming `$abc$1070$g041' to `_268_'. |
| renaming `$abc$1070$g042' to `_269_'. |
| renaming `$abc$1070$g043' to `_270_'. |
| renaming `$abc$1070$g044' to `_271_'. |
| renaming `$abc$1070$g045' to `_272_'. |
| renaming `$abc$1070$g046' to `_273_'. |
| renaming `$abc$1070$g047' to `_274_'. |
| renaming `$abc$1070$g048' to `_275_'. |
| renaming `$abc$1070$g049' to `_276_'. |
| renaming `$abc$1070$g050' to `_277_'. |
| renaming `$abc$1070$g051' to `_278_'. |
| renaming `$abc$1070$g052' to `_279_'. |
| renaming `$abc$1070$g053' to `_280_'. |
| renaming `$abc$1070$g054' to `_281_'. |
| renaming `$abc$1070$g055' to `_282_'. |
| renaming `$abc$1070$g056' to `_283_'. |
| renaming `$abc$1070$g057' to `_284_'. |
| renaming `$abc$1070$g058' to `_285_'. |
| renaming `$abc$1070$g059' to `_286_'. |
| renaming `$abc$1070$g060' to `_287_'. |
| renaming `$abc$1070$g061' to `_288_'. |
| renaming `$abc$1070$g062' to `_289_'. |
| renaming `$abc$1070$g063' to `_290_'. |
| renaming `$abc$1070$g064' to `_291_'. |
| renaming `$abc$1070$g065' to `_292_'. |
| renaming `$abc$1070$g066' to `_293_'. |
| renaming `$abc$1070$g067' to `_294_'. |
| renaming `$abc$1070$g068' to `_295_'. |
| renaming `$abc$1070$g069' to `_296_'. |
| renaming `$abc$1070$g070' to `_297_'. |
| renaming `$abc$1070$g071' to `_298_'. |
| renaming `$abc$1070$g072' to `_299_'. |
| renaming `$abc$1070$g073' to `_300_'. |
| renaming `$abc$1070$g074' to `_301_'. |
| renaming `$abc$1070$g075' to `_302_'. |
| renaming `$abc$1070$g076' to `_303_'. |
| renaming `$abc$1070$g077' to `_304_'. |
| renaming `$abc$1070$g078' to `_305_'. |
| renaming `$abc$1070$g079' to `_306_'. |
| renaming `$abc$1070$g080' to `_307_'. |
| renaming `$abc$1070$g081' to `_308_'. |
| renaming `$abc$1070$g082' to `_309_'. |
| renaming `$abc$1070$g083' to `_310_'. |
| renaming `$abc$1070$g084' to `_311_'. |
| renaming `$abc$1070$g085' to `_312_'. |
| renaming `$abc$1070$g086' to `_313_'. |
| renaming `$abc$1070$g087' to `_314_'. |
| renaming `$abc$1070$g088' to `_315_'. |
| renaming `$abc$1070$g089' to `_316_'. |
| renaming `$abc$1070$g090' to `_317_'. |
| renaming `$abc$1070$g091' to `_318_'. |
| renaming `$abc$1070$g092' to `_319_'. |
| renaming `$abc$1070$g093' to `_320_'. |
| renaming `$abc$1070$g094' to `_321_'. |
| renaming `$abc$1070$g095' to `_322_'. |
| renaming `$abc$1070$g096' to `_323_'. |
| renaming `$abc$1070$g097' to `_324_'. |
| renaming `$abc$1070$g098' to `_325_'. |
| renaming `$abc$1070$g099' to `_326_'. |
| renaming `$abc$1070$g100' to `_327_'. |
| renaming `$abc$1070$g101' to `_328_'. |
| renaming `$abc$1070$g102' to `_329_'. |
| renaming `$abc$1070$g103' to `_330_'. |
| renaming `$abc$1070$g104' to `_331_'. |
| renaming `$abc$1070$g105' to `_332_'. |
| renaming `$abc$1070$g106' to `_333_'. |
| renaming `$abc$1070$g107' to `_334_'. |
| renaming `$abc$1070$g108' to `_335_'. |
| renaming `$abc$1070$g109' to `_336_'. |
| renaming `$abc$1070$g110' to `_337_'. |
| renaming `$abc$1070$g111' to `_338_'. |
| renaming `$abc$1070$g112' to `_339_'. |
| renaming `$abc$1070$g113' to `_340_'. |
| renaming `$abc$1070$g114' to `_341_'. |
| renaming `$abc$1070$g115' to `_342_'. |
| renaming `$abc$1070$g116' to `_343_'. |
| renaming `$abc$1070$g117' to `_344_'. |
| renaming `$abc$1070$g118' to `_345_'. |
| renaming `$abc$1070$g119' to `_346_'. |
| renaming `$abc$1070$g120' to `_347_'. |
| renaming `$abc$1070$g121' to `_348_'. |
| renaming `$abc$1070$g122' to `_349_'. |
| renaming `$abc$1070$g123' to `_350_'. |
| renaming `$abc$1070$g124' to `_351_'. |
| renaming `$abc$1070$g125' to `_352_'. |
| renaming `$abc$1070$g126' to `_353_'. |
| renaming `$abc$1070$g127' to `_354_'. |
| renaming `$abc$1070$g128' to `_355_'. |
| renaming `$abc$1070$g129' to `_356_'. |
| renaming `$abc$1070$g130' to `_357_'. |
| renaming `$abc$1070$g131' to `_358_'. |
| renaming `$abc$1070$g132' to `_359_'. |
| renaming `$abc$1070$g133' to `_360_'. |
| renaming `$abc$1070$g134' to `_361_'. |
| renaming `$abc$1070$g135' to `_362_'. |
| renaming `$abc$1070$g136' to `_363_'. |
| renaming `$abc$1070$g137' to `_364_'. |
| renaming `$abc$1070$g138' to `_365_'. |
| renaming `$abc$1070$g139' to `_366_'. |
| renaming `$abc$1070$g140' to `_367_'. |
| renaming `$abc$1070$g141' to `_368_'. |
| renaming `$abc$1070$g142' to `_369_'. |
| renaming `$abc$1070$g143' to `_370_'. |
| renaming `$abc$1070$g144' to `_371_'. |
| renaming `$abc$1070$g145' to `_372_'. |
| renaming `$abc$1070$g146' to `_373_'. |
| renaming `$abc$1070$g147' to `_374_'. |
| renaming `$abc$1070$g148' to `_375_'. |
| renaming `$abc$1070$g149' to `_376_'. |
| renaming `$abc$1070$g150' to `_377_'. |
| renaming `$abc$1070$g151' to `_378_'. |
| renaming `$abc$1070$g152' to `_379_'. |
| renaming `$abc$1070$g153' to `_380_'. |
| renaming `$abc$1070$g154' to `_381_'. |
| renaming `$abc$1070$g155' to `_382_'. |
| renaming `$abc$1070$g156' to `_383_'. |
| renaming `$abc$1070$g157' to `_384_'. |
| renaming `$abc$1070$g158' to `_385_'. |
| renaming `$abc$1070$g159' to `_386_'. |
| renaming `$abc$1070$g160' to `_387_'. |
| renaming `$abc$1070$g161' to `_388_'. |
| renaming `$abc$1070$g162' to `_389_'. |
| renaming `$abc$1070$g163' to `_390_'. |
| renaming `$abc$1070$g164' to `_391_'. |
| renaming `$abc$1070$g165' to `_392_'. |
| renaming `$abc$1070$g166' to `_393_'. |
| renaming `$abc$1070$g167' to `_394_'. |
| renaming `$abc$1070$g168' to `_395_'. |
| renaming `$abc$1070$g169' to `_396_'. |
| renaming `$abc$1070$g170' to `_397_'. |
| renaming `$abc$1070$g171' to `_398_'. |
| renaming `$abc$1070$g172' to `_399_'. |
| renaming `$abc$1070$g173' to `_400_'. |
| renaming `$abc$1070$g174' to `_401_'. |
| renaming `$abc$1070$g175' to `_402_'. |
| renaming `$abc$1070$g176' to `_403_'. |
| renaming `$abc$1070$g177' to `_404_'. |
| renaming `$abc$1070$g178' to `_405_'. |
| renaming `$abc$1070$g179' to `_406_'. |
| renaming `$abc$1070$g180' to `_407_'. |
| renaming `$abc$1070$g181' to `_408_'. |
| renaming `$abc$1070$g182' to `_409_'. |
| renaming `$abc$1070$g183' to `_410_'. |
| renaming `$abc$1070$g184' to `_411_'. |
| renaming `$abc$1070$g185' to `_412_'. |
| renaming `$abc$1070$g186' to `_413_'. |
| renaming `$abc$1070$g187' to `_414_'. |
| renaming `$abc$1070$g188' to `_415_'. |
| renaming `$abc$1070$g189' to `_416_'. |
| renaming `$abc$1070$g190' to `_417_'. |
| renaming `$abc$1070$g191' to `_418_'. |
| renaming `$abc$1070$g192' to `_419_'. |
| renaming `$abc$1070$g193' to `_420_'. |
| renaming `$abc$1070$g194' to `_421_'. |
| renaming `$abc$1070$g195' to `_422_'. |
| renaming `$abc$1070$g196' to `_423_'. |
| renaming `$abc$1070$g197' to `_424_'. |
| renaming `$abc$1070$g198' to `_425_'. |
| renaming `$abc$1070$g199' to `_426_'. |
| renaming `$abc$1070$g200' to `_427_'. |
| renaming `$abc$1070$g201' to `_428_'. |
| renaming `$abc$1070$g202' to `_429_'. |
| renaming `$abc$1070$g203' to `_430_'. |
| renaming `$abc$1070$g204' to `_431_'. |
| renaming `$abc$1070$g205' to `_432_'. |
| renaming `$abc$1070$g206' to `_433_'. |
| renaming `$abc$1070$g207' to `_434_'. |
| renaming `$abc$1070$g208' to `_435_'. |
| renaming `$abc$1070$g209' to `_436_'. |
| renaming `$abc$1070$g210' to `_437_'. |
| renaming `$abc$1070$g211' to `_438_'. |
| renaming `$abc$1070$g212' to `_439_'. |
| renaming `$abc$1070$g213' to `_440_'. |
| renaming `$abc$1070$g214' to `_441_'. |
| renaming `$abc$1070$g215' to `_442_'. |
| renaming `$abc$1070$g216' to `_443_'. |
| renaming `$abc$1070$g217' to `_444_'. |
| renaming `$abc$1070$g218' to `_445_'. |
| renaming `$abc$1070$g219' to `_446_'. |
| renaming `$abc$1070$g220' to `_447_'. |
| renaming `$abc$1070$g221' to `_448_'. |
| renaming `$abc$1070$g222' to `_449_'. |
| renaming `$abc$1070$g223' to `_450_'. |
| renaming `$abc$1070$g224' to `_451_'. |
| renaming `$abc$1070$g225' to `_452_'. |
| renaming `$abc$1070$g226' to `_453_'. |
| renaming `$abc$1070$g227' to `_454_'. |
| renaming `$abc$1070$g228' to `_455_'. |
| renaming `$abc$1070$g229' to `_456_'. |
| renaming `$abc$1070$g230' to `_457_'. |
| renaming `$abc$1070$g231' to `_458_'. |
| renaming `$abc$1070$g232' to `_459_'. |
| renaming `$abc$1070$g233' to `_460_'. |
| renaming `$abc$1070$g234' to `_461_'. |
| renaming `$abc$1070$g235' to `_462_'. |
| renaming `$abc$1070$g236' to `_463_'. |
| renaming `$abc$1070$g237' to `_464_'. |
| renaming `$abc$1070$g238' to `_465_'. |
| renaming `$abc$1070$g239' to `_466_'. |
| renaming `$abc$1070$g240' to `_467_'. |
| renaming `$abc$1070$g241' to `_468_'. |
| renaming `$abc$1070$g242' to `_469_'. |
| renaming `$abc$1070$g243' to `_470_'. |
| renaming `$abc$1070$g244' to `_471_'. |
| renaming `$abc$1070$g245' to `_472_'. |
| renaming `$abc$1070$g246' to `_473_'. |
| renaming `$abc$1070$g247' to `_474_'. |
| renaming `$abc$1070$g248' to `_475_'. |
| renaming `$abc$1070$g249' to `_476_'. |
| renaming `$abc$1070$g250' to `_477_'. |
| renaming `$abc$1070$g251' to `_478_'. |
| renaming `$abc$1070$g252' to `_479_'. |
| renaming `$abc$1070$g253' to `_480_'. |
| renaming `$abc$1070$g254' to `_481_'. |
| renaming `$abc$1070$g255' to `_482_'. |
| renaming `$abc$1070$g256' to `_483_'. |
| renaming `$abc$1070$g257' to `_484_'. |
| renaming `$abc$1070$g258' to `_485_'. |
| renaming `$abc$1070$g259' to `_486_'. |
| renaming `$abc$1070$g260' to `_487_'. |
| renaming `$abc$1070$g261' to `_488_'. |
| renaming `$abc$1070$g262' to `_489_'. |
| renaming `$abc$1070$g263' to `_490_'. |
| renaming `$abc$1070$g264' to `_491_'. |
| renaming `$abc$1070$g265' to `_492_'. |
| renaming `$abc$1070$g266' to `_493_'. |
| renaming `$abc$1070$g267' to `_494_'. |
| renaming `$abc$1070$g268' to `_495_'. |
| renaming `$abc$1070$g269' to `_496_'. |
| renaming `$abc$1070$n126' to `_011_'. |
| renaming `$abc$1070$n127' to `_012_'. |
| renaming `$abc$1070$n129_1' to `_013_'. |
| renaming `$abc$1070$n130_1' to `_014_'. |
| renaming `$abc$1070$n131_1' to `_015_'. |
| renaming `$abc$1070$n132_1' to `_016_'. |
| renaming `$abc$1070$n133_1' to `_017_'. |
| renaming `$abc$1070$n134_1' to `_018_'. |
| renaming `$abc$1070$n135_1' to `_019_'. |
| renaming `$abc$1070$n136_1' to `_020_'. |
| renaming `$abc$1070$n137' to `_021_'. |
| renaming `$abc$1070$n139' to `_022_'. |
| renaming `$abc$1070$n140_1' to `_023_'. |
| renaming `$abc$1070$n142_1' to `_024_'. |
| renaming `$abc$1070$n143' to `_025_'. |
| renaming `$abc$1070$n145' to `_026_'. |
| renaming `$abc$1070$n146_1' to `_027_'. |
| renaming `$abc$1070$n148_1' to `_028_'. |
| renaming `$abc$1070$n149' to `_029_'. |
| renaming `$abc$1070$n151' to `_030_'. |
| renaming `$abc$1070$n152_1' to `_031_'. |
| renaming `$abc$1070$n154' to `_032_'. |
| renaming `$abc$1070$n155' to `_033_'. |
| renaming `$abc$1070$n157' to `_034_'. |
| renaming `$abc$1070$n158' to `_035_'. |
| renaming `$abc$1070$n160' to `_036_'. |
| renaming `$abc$1070$n161' to `_037_'. |
| renaming `$abc$1070$n162_1' to `_038_'. |
| renaming `$abc$1070$n163_1' to `_039_'. |
| renaming `$abc$1070$n164_1' to `_040_'. |
| renaming `$abc$1070$n166_1' to `_041_'. |
| renaming `$abc$1070$n167_1' to `_042_'. |
| renaming `$abc$1070$n169_1' to `_043_'. |
| renaming `$abc$1070$n170_1' to `_044_'. |
| renaming `$abc$1070$n172_1' to `_045_'. |
| renaming `$abc$1070$n173' to `_046_'. |
| renaming `$abc$1070$n175' to `_047_'. |
| renaming `$abc$1070$n176_1' to `_048_'. |
| renaming `$abc$1070$n178' to `_049_'. |
| renaming `$abc$1070$n179' to `_050_'. |
| renaming `$abc$1070$n181' to `_051_'. |
| renaming `$abc$1070$n182' to `_052_'. |
| renaming `$abc$1070$n184' to `_053_'. |
| renaming `$abc$1070$n185' to `_054_'. |
| renaming `$abc$1070$n187' to `_055_'. |
| renaming `$abc$1070$n188' to `_056_'. |
| renaming `$abc$1070$n189' to `_057_'. |
| renaming `$abc$1070$n190' to `_058_'. |
| renaming `$abc$1070$n192' to `_059_'. |
| renaming `$abc$1070$n193' to `_060_'. |
| renaming `$abc$1070$n195_1' to `_061_'. |
| renaming `$abc$1070$n196_1' to `_062_'. |
| renaming `$abc$1070$n198_1' to `_063_'. |
| renaming `$abc$1070$n199' to `_064_'. |
| renaming `$abc$1070$n201_1' to `_065_'. |
| renaming `$abc$1070$n202_1' to `_066_'. |
| renaming `$abc$1070$n204_1' to `_067_'. |
| renaming `$abc$1070$n205_1' to `_068_'. |
| renaming `$abc$1070$n207_1' to `_069_'. |
| renaming `$abc$1070$n208' to `_070_'. |
| renaming `$abc$1070$n210_1' to `_071_'. |
| renaming `$abc$1070$n211' to `_072_'. |
| renaming `$abc$1070$n213_1' to `_073_'. |
| renaming `$abc$1070$n214' to `_074_'. |
| renaming `$abc$1070$n215' to `_075_'. |
| renaming `$abc$1070$n216' to `_076_'. |
| renaming `$abc$1070$n218' to `_077_'. |
| renaming `$abc$1070$n219' to `_078_'. |
| renaming `$abc$1070$n221' to `_079_'. |
| renaming `$abc$1070$n222' to `_080_'. |
| renaming `$abc$1070$n224' to `_081_'. |
| renaming `$abc$1070$n225' to `_082_'. |
| renaming `$abc$1070$n227' to `_083_'. |
| renaming `$abc$1070$n228' to `_084_'. |
| renaming `$abc$1070$n230' to `_085_'. |
| renaming `$abc$1070$n231' to `_086_'. |
| renaming `$abc$1070$n233_1' to `_087_'. |
| renaming `$abc$1070$n234' to `_088_'. |
| renaming `$abc$1070$n236_1' to `_089_'. |
| renaming `$abc$1070$n237' to `_090_'. |
| renaming `$abc$1070$n239' to `_091_'. |
| renaming `$abc$1070$n240_1' to `_092_'. |
| renaming `$abc$1070$n241' to `_093_'. |
| renaming `$abc$1070$n242_1' to `_094_'. |
| renaming `$abc$1070$n243' to `_095_'. |
| renaming `$abc$1070$n244_1' to `_096_'. |
| renaming `$abc$1070$n246_1' to `_097_'. |
| renaming `$abc$1070$n248_1' to `_098_'. |
| renaming `$abc$1070$n250_1' to `_099_'. |
| renaming `$abc$1070$n251' to `_100_'. |
| renaming `$abc$1070$n252_1' to `_101_'. |
| renaming `$abc$1070$n253' to `_102_'. |
| renaming `$abc$1070$n254_1' to `_103_'. |
| renaming `$abc$1070$n256' to `_104_'. |
| renaming `$abc$1070$n257' to `_105_'. |
| renaming `$abc$1070$n258' to `_106_'. |
| renaming `$abc$1070$n260' to `_107_'. |
| renaming `$abc$1070$n261' to `_108_'. |
| renaming `$abc$1070$n262' to `_109_'. |
| renaming `$abc$1070$n264' to `_110_'. |
| renaming `$abc$1070$n265' to `_111_'. |
| renaming `$abc$1070$n266' to `_112_'. |
| renaming `$abc$1070$n268' to `_113_'. |
| renaming `$abc$1070$n269' to `_114_'. |
| renaming `$abc$1070$n271' to `_115_'. |
| renaming `$abc$1070$n272' to `_116_'. |
| renaming `$abc$1070$n273' to `_117_'. |
| renaming `$abc$1070$n275' to `_118_'. |
| renaming `$abc$1070$n276' to `_119_'. |
| renaming `$abc$1070$n277' to `_120_'. |
| renaming `$abc$1070$n280' to `_121_'. |
| renaming `$abc$1070$n282' to `_122_'. |
| renaming `$abc$1070$n284' to `_123_'. |
| renaming `$abc$1070$n285' to `_124_'. |
| renaming `$abc$1070$n286' to `_125_'. |
| renaming `$abc$1070$n287' to `_126_'. |
| renaming `$abc$1070$n288' to `_127_'. |
| renaming `$abc$1070$n292' to `_128_'. |
| renaming `$abc$1070$n293' to `_129_'. |
| renaming `$abc$1070$n294' to `_130_'. |
| renaming `$abc$1070$n295' to `_131_'. |
| renaming `$abc$1070$n296' to `_132_'. |
| renaming `$abc$1070$n297' to `_133_'. |
| renaming `$abc$1070$n298' to `_134_'. |
| renaming `$abc$1070$n299' to `_135_'. |
| renaming `$abc$1070$n300' to `_136_'. |
| renaming `$abc$1070$n301' to `_137_'. |
| renaming `$abc$1070$n302' to `_138_'. |
| renaming `$abc$1070$n303' to `_139_'. |
| renaming `$abc$1070$n304' to `_140_'. |
| renaming `$abc$1070$n305' to `_141_'. |
| renaming `$abc$1070$n307' to `_142_'. |
| renaming `$abc$1070$n308' to `_143_'. |
| renaming `$abc$1070$n309' to `_144_'. |
| renaming `$abc$1070$n310' to `_145_'. |
| renaming `$abc$1070$n311' to `_146_'. |
| renaming `$abc$1070$n312' to `_147_'. |
| renaming `$abc$1070$n313' to `_148_'. |
| renaming `$abc$1070$n314' to `_149_'. |
| renaming `$abc$1070$n315' to `_150_'. |
| renaming `$abc$1070$n316' to `_151_'. |
| renaming `$abc$1070$n317' to `_152_'. |
| renaming `$abc$1070$n318' to `_153_'. |
| renaming `$abc$1070$n319' to `_154_'. |
| renaming `$abc$1070$n321' to `_155_'. |
| renaming `$abc$1070$n322' to `_156_'. |
| renaming `$abc$1070$n323' to `_157_'. |
| renaming `$abc$1070$n324' to `_158_'. |
| renaming `$abc$1070$n325' to `_159_'. |
| renaming `$abc$1070$n326' to `_160_'. |
| renaming `$abc$1070$n327' to `_161_'. |
| renaming `$abc$1070$n328' to `_162_'. |
| renaming `$abc$1070$n329' to `_163_'. |
| renaming `$abc$1070$n330' to `_164_'. |
| renaming `$abc$1070$n331_1' to `_165_'. |
| renaming `$abc$1070$n333_1' to `_166_'. |
| renaming `$abc$1070$n334_1' to `_167_'. |
| renaming `$abc$1070$n335_1' to `_168_'. |
| renaming `$abc$1070$n336_1' to `_169_'. |
| renaming `$abc$1070$n337_1' to `_170_'. |
| renaming `$abc$1070$n338_1' to `_171_'. |
| renaming `$abc$1070$n339' to `_172_'. |
| renaming `$abc$1070$n340' to `_173_'. |
| renaming `$abc$1070$n341' to `_174_'. |
| renaming `$abc$1070$n342' to `_175_'. |
| renaming `$abc$1070$n343' to `_176_'. |
| renaming `$abc$1070$n345' to `_177_'. |
| renaming `$abc$1070$n346' to `_178_'. |
| renaming `$abc$1070$n347' to `_179_'. |
| renaming `$abc$1070$n348' to `_180_'. |
| renaming `$abc$1070$n349' to `_181_'. |
| renaming `$abc$1070$n350' to `_182_'. |
| renaming `$abc$1070$n351' to `_183_'. |
| renaming `$abc$1070$n352' to `_184_'. |
| renaming `$abc$1070$n353' to `_185_'. |
| renaming `$abc$1070$n354' to `_186_'. |
| renaming `$abc$1070$n355' to `_187_'. |
| renaming `$abc$1070$n357' to `_188_'. |
| renaming `$abc$1070$n358' to `_189_'. |
| renaming `$abc$1070$n359' to `_190_'. |
| renaming `$abc$1070$n360' to `_191_'. |
| renaming `$abc$1070$n361' to `_192_'. |
| renaming `$abc$1070$n362' to `_193_'. |
| renaming `$abc$1070$n363' to `_194_'. |
| renaming `$abc$1070$n364' to `_195_'. |
| renaming `$abc$1070$n365' to `_196_'. |
| renaming `$abc$1070$n366' to `_197_'. |
| renaming `$abc$1070$n367' to `_198_'. |
| renaming `$abc$1070$n368' to `_199_'. |
| renaming `$abc$1070$n369' to `_200_'. |
| renaming `$abc$1070$n371' to `_201_'. |
| renaming `$abc$1070$n372' to `_202_'. |
| renaming `$abc$1070$n373' to `_203_'. |
| renaming `$abc$1070$n374' to `_204_'. |
| renaming `$abc$1070$n375' to `_205_'. |
| renaming `$abc$1070$n376' to `_206_'. |
| renaming `$abc$1070$n377' to `_207_'. |
| renaming `$abc$1070$n378' to `_208_'. |
| renaming `$abc$1070$n379' to `_209_'. |
| renaming `$abc$1070$n380' to `_210_'. |
| renaming `$abc$1070$n381' to `_211_'. |
| renaming `$abc$1070$n382' to `_212_'. |
| renaming `$abc$1070$n383' to `_213_'. |
| renaming `$abc$1070$n385' to `_214_'. |
| renaming `$abc$1070$n386' to `_215_'. |
| renaming `$abc$1070$n387' to `_216_'. |
| renaming `$abc$1070$n388' to `_217_'. |
| renaming `$abc$1070$n389' to `_218_'. |
| renaming `$abc$1070$n390' to `_219_'. |
| renaming `$abc$1070$n391' to `_220_'. |
| renaming `$abc$1070$n392' to `_221_'. |
| renaming `$abc$1070$n393' to `_222_'. |
| renaming `$abc$1070$n394' to `_223_'. |
| renaming `$abc$1070$n395' to `_224_'. |
| renaming `$abc$1070$n396' to `_225_'. |
| renaming `$abc$1070$n397' to `_226_'. |
| renaming `$procdff$895.V[0].ff' to `_497_'. |
| renaming `$procdff$896.V[0].ff' to `_498_'. |
| renaming `$procdff$896.V[1].ff' to `_499_'. |
| renaming `$procdff$896.V[2].ff' to `_500_'. |
| renaming `$procdff$896.V[3].ff' to `_501_'. |
| renaming `$procdff$896.V[4].ff' to `_502_'. |
| renaming `$procdff$896.V[5].ff' to `_503_'. |
| renaming `$procdff$896.V[6].ff' to `_504_'. |
| renaming `$procdff$896.V[7].ff' to `_505_'. |
| renaming `$procdff$897.V[0].P.PN.PN0.ff' to `_506_'. |
| renaming `$procdff$897.V[1].P.PN.PN0.ff' to `_507_'. |
| renaming `$procdff$897.V[2].P.PN.PN0.ff' to `_508_'. |
| renaming `$procdff$897.V[3].P.PN.PN0.ff' to `_509_'. |
| renaming `$procdff$897.V[4].P.PN.PN0.ff' to `_510_'. |
| renaming `$procdff$897.V[5].P.PN.PN0.ff' to `_511_'. |
| renaming `$procdff$897.V[6].P.PN.PN0.ff' to `_512_'. |
| renaming `$procdff$897.V[7].P.PN.PN0.ff' to `_513_'. |
| renaming `$procdff$898.V[0].P.PN.PN1.ff' to `_514_'. |
| renaming `$procdff$898.V[10].P.PN.PN1.ff' to `_515_'. |
| renaming `$procdff$898.V[11].P.PN.PN1.ff' to `_516_'. |
| renaming `$procdff$898.V[12].P.PN.PN1.ff' to `_517_'. |
| renaming `$procdff$898.V[13].P.PN.PN1.ff' to `_518_'. |
| renaming `$procdff$898.V[14].P.PN.PN1.ff' to `_519_'. |
| renaming `$procdff$898.V[15].P.PN.PN1.ff' to `_520_'. |
| renaming `$procdff$898.V[1].P.PN.PN1.ff' to `_521_'. |
| renaming `$procdff$898.V[2].P.PN.PN1.ff' to `_522_'. |
| renaming `$procdff$898.V[3].P.PN.PN1.ff' to `_523_'. |
| renaming `$procdff$898.V[4].P.PN.PN1.ff' to `_524_'. |
| renaming `$procdff$898.V[5].P.PN.PN1.ff' to `_525_'. |
| renaming `$procdff$898.V[6].P.PN.PN1.ff' to `_526_'. |
| renaming `$procdff$898.V[7].P.PN.PN1.ff' to `_527_'. |
| renaming `$procdff$898.V[8].P.PN.PN1.ff' to `_528_'. |
| renaming `$procdff$898.V[9].P.PN.PN1.ff' to `_529_'. |
| renaming `$procdff$899.V[0].P.PN.PN0.ff' to `_530_'. |
| renaming `$procdff$899.V[1].P.PN.PN0.ff' to `_531_'. |
| renaming `$procdff$899.V[2].P.PN.PN0.ff' to `_532_'. |
| renaming `$procdff$899.V[3].P.PN.PN0.ff' to `_533_'. |
| renaming `$procdff$899.V[4].P.PN.PN0.ff' to `_534_'. |
| renaming `$procdff$899.V[5].P.PN.PN0.ff' to `_535_'. |
| renaming `$procdff$899.V[6].P.PN.PN0.ff' to `_536_'. |
| renaming `$procdff$899.V[7].P.PN.PN0.ff' to `_537_'. |
| renaming `$procdff$900.V[0].P.PN.PN0.ff' to `_538_'. |
| renaming `$procdff$900.V[1].P.PN.PN0.ff' to `_539_'. |
| renaming `$procdff$900.V[2].P.PN.PN0.ff' to `_540_'. |
| renaming `$procdff$900.V[3].P.PN.PN0.ff' to `_541_'. |
| renaming `$procdff$900.V[4].P.PN.PN0.ff' to `_542_'. |
| renaming `$procdff$900.V[5].P.PN.PN0.ff' to `_543_'. |
| renaming `$procdff$900.V[6].P.PN.PN0.ff' to `_544_'. |
| renaming `$procdff$900.V[7].P.PN.PN0.ff' to `_545_'. |
| renaming `$procdff$901.V[0].P.PN.PN0.ff' to `_546_'. |
| renaming `$procdff$902.V[0].P.PN.PN0.ff' to `_547_'. |
| renaming `$procdff$903.V[0].P.PN.PN0.ff' to `_548_'. |
| renaming `$procdff$904.V[0].P.PN.PN0.ff' to `_549_'. |
| renaming `$procdff$905.V[0].P.PN.PN0.ff' to `_550_'. |
| |
| READY. |
