| |
| /-----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \-----------------------------------------------------------------------------/ |
| |
| |
| -- Executing script file `scripts/synth.ys' -- |
| |
| 1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/sasc_brg.v |
| Parsing Verilog input from `rtl/sasc_brg.v' to AST representation. |
| Generating RTLIL representation for module `\sasc_brg'. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/sasc_fifo4.v |
| Parsing Verilog input from `rtl/sasc_fifo4.v' to AST representation. |
| Generating RTLIL representation for module `\sasc_fifo4'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing Verilog-2005 frontend. |
| Full command line: read_verilog rtl/sasc_top.v |
| Parsing Verilog input from `rtl/sasc_top.v' to AST representation. |
| Generating RTLIL representation for module `\sasc_top'. |
| Note: Assuming pure combinatorial block at rtl/sasc_top.v:267 in |
| compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending |
| use of @* instead of @(...) for better match of synthesis and simulation. |
| Successfully finished Verilog frontend. |
| |
| 4. Executing HIERARCHY pass (managing design hierarchy). |
| Full command line: hierarchy -top sasc_top |
| Top module: \sasc_top |
| Used module: \sasc_fifo4 |
| Removing unused module `\sasc_brg'. |
| Removed 1 unused modules. |
| Top module: \sasc_top |
| Used module: \sasc_fifo4 |
| Removed 0 unused modules. |
| |
| -- Executing script file `../scripts/generic.ys' -- |
| |
| 5. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6. Executing PROC pass (convert processes to netlists). |
| |
| 6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed 1 dead cases from process $proc$rtl/sasc_top.v:267$100 in module \sasc_top. |
| Removed a total of 1 dead cases. |
| |
| 6.3. Executing PROC_ARST pass (detect async resets in processes). |
| Found async reset \rst in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:103$32'. |
| Found async reset \rst in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:93$28'. |
| Found async reset \rst in `\sasc_top.$proc$rtl/sasc_top.v:262$98'. |
| |
| 6.4. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:103$32'. |
| creating decoder for signal `$0\rp[1:0]'. |
| Creating decoders for process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| creating decoder for signal `$0$memwr$\mem$rtl/sasc_fifo4.v:117$27_ADDR[1:0]'. |
| creating decoder for signal `$0$memwr$\mem$rtl/sasc_fifo4.v:117$27_DATA[7:0]'. |
| creating decoder for signal `$0$memwr$\mem$rtl/sasc_fifo4.v:117$27_EN[0:0]'. |
| Creating decoders for process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:124$42'. |
| creating decoder for signal `$0\gb[0:0]'. |
| Creating decoders for process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:93$28'. |
| creating decoder for signal `$0\wp[1:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:163$47'. |
| creating decoder for signal `$0\txf_empty_r[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:168$49'. |
| creating decoder for signal `$0\load[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:171$55'. |
| creating decoder for signal `$0\load_r[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:176$57'. |
| creating decoder for signal `$0\hold_reg[9:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:181$59'. |
| creating decoder for signal `$0\txd_o[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:188$62'. |
| creating decoder for signal `$0\tx_bit_cnt[3:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:195$66'. |
| creating decoder for signal `$0\shift_en[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:198$68'. |
| creating decoder for signal `$0\shift_en_r[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:208$70'. |
| creating decoder for signal `$0\rxd_s[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:211$71'. |
| creating decoder for signal `$0\rxd_r[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:216$75'. |
| creating decoder for signal `$0\rx_bit_cnt[3:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:223$81'. |
| creating decoder for signal `$0\rx_go[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:226$83'. |
| creating decoder for signal `$0\rx_valid[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:229$85'. |
| creating decoder for signal `$0\rx_valid_r[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:234$90'. |
| creating decoder for signal `$0\rxr[9:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:237$92'. |
| creating decoder for signal `$0\rts_o[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:248$93'. |
| creating decoder for signal `$0\rxd_r1[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:251$94'. |
| creating decoder for signal `$0\rxd_r2[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:254$95'. |
| creating decoder for signal `$0\change[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:262$98'. |
| creating decoder for signal `$0\dpll_state[1:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:267$100'. |
| creating decoder for signal `$0\dpll_next_state[1:0]'. |
| creating decoder for signal `$0\rx_sio_ce_d[0:0]'. |
| creating decoder for signal `$1\rx_sio_ce_d[0:0]'. |
| creating decoder for signal `$1\dpll_next_state[1:0]'. |
| creating decoder for signal `$2\dpll_next_state[1:0]'. |
| creating decoder for signal `$3\dpll_next_state[1:0]'. |
| creating decoder for signal `$4\dpll_next_state[1:0]'. |
| creating decoder for signal `$5\dpll_next_state[1:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:290$101'. |
| creating decoder for signal `$0\rx_sio_ce_r1[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:293$102'. |
| creating decoder for signal `$0\rx_sio_ce_r2[0:0]'. |
| Creating decoders for process `\sasc_top.$proc$rtl/sasc_top.v:296$103'. |
| creating decoder for signal `$0\rx_sio_ce[0:0]'. |
| |
| 6.5. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\sasc_fifo4.\rp' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:103$32'. |
| created $adff cell `$procdff$321' with positive edge clock and negative level reset. |
| Creating register for signal `\sasc_fifo4.$memwr$\mem$rtl/sasc_fifo4.v:117$27_ADDR' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| created $dff cell `$procdff$322' with positive edge clock. |
| Creating register for signal `\sasc_fifo4.$memwr$\mem$rtl/sasc_fifo4.v:117$27_DATA' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| created $dff cell `$procdff$323' with positive edge clock. |
| Creating register for signal `\sasc_fifo4.$memwr$\mem$rtl/sasc_fifo4.v:117$27_EN' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| created $dff cell `$procdff$324' with positive edge clock. |
| Creating register for signal `\sasc_fifo4.\gb' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:124$42'. |
| created $dff cell `$procdff$325' with positive edge clock. |
| Creating register for signal `\sasc_fifo4.\wp' using process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:93$28'. |
| created $adff cell `$procdff$326' with positive edge clock and negative level reset. |
| Creating register for signal `\sasc_top.\txf_empty_r' using process `\sasc_top.$proc$rtl/sasc_top.v:163$47'. |
| created $dff cell `$procdff$327' with positive edge clock. |
| Creating register for signal `\sasc_top.\load' using process `\sasc_top.$proc$rtl/sasc_top.v:168$49'. |
| created $dff cell `$procdff$328' with positive edge clock. |
| Creating register for signal `\sasc_top.\load_r' using process `\sasc_top.$proc$rtl/sasc_top.v:171$55'. |
| created $dff cell `$procdff$329' with positive edge clock. |
| Creating register for signal `\sasc_top.\hold_reg' using process `\sasc_top.$proc$rtl/sasc_top.v:176$57'. |
| created $dff cell `$procdff$330' with positive edge clock. |
| Creating register for signal `\sasc_top.\txd_o' using process `\sasc_top.$proc$rtl/sasc_top.v:181$59'. |
| created $dff cell `$procdff$331' with positive edge clock. |
| Creating register for signal `\sasc_top.\tx_bit_cnt' using process `\sasc_top.$proc$rtl/sasc_top.v:188$62'. |
| created $dff cell `$procdff$332' with positive edge clock. |
| Creating register for signal `\sasc_top.\shift_en' using process `\sasc_top.$proc$rtl/sasc_top.v:195$66'. |
| created $dff cell `$procdff$333' with positive edge clock. |
| Creating register for signal `\sasc_top.\shift_en_r' using process `\sasc_top.$proc$rtl/sasc_top.v:198$68'. |
| created $dff cell `$procdff$334' with positive edge clock. |
| Creating register for signal `\sasc_top.\rxd_s' using process `\sasc_top.$proc$rtl/sasc_top.v:208$70'. |
| created $dff cell `$procdff$335' with positive edge clock. |
| Creating register for signal `\sasc_top.\rxd_r' using process `\sasc_top.$proc$rtl/sasc_top.v:211$71'. |
| created $dff cell `$procdff$336' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_bit_cnt' using process `\sasc_top.$proc$rtl/sasc_top.v:216$75'. |
| created $dff cell `$procdff$337' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_go' using process `\sasc_top.$proc$rtl/sasc_top.v:223$81'. |
| created $dff cell `$procdff$338' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_valid' using process `\sasc_top.$proc$rtl/sasc_top.v:226$83'. |
| created $dff cell `$procdff$339' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_valid_r' using process `\sasc_top.$proc$rtl/sasc_top.v:229$85'. |
| created $dff cell `$procdff$340' with positive edge clock. |
| Creating register for signal `\sasc_top.\rxr' using process `\sasc_top.$proc$rtl/sasc_top.v:234$90'. |
| created $dff cell `$procdff$341' with positive edge clock. |
| Creating register for signal `\sasc_top.\rts_o' using process `\sasc_top.$proc$rtl/sasc_top.v:237$92'. |
| created $dff cell `$procdff$342' with positive edge clock. |
| Creating register for signal `\sasc_top.\rxd_r1' using process `\sasc_top.$proc$rtl/sasc_top.v:248$93'. |
| created $dff cell `$procdff$343' with positive edge clock. |
| Creating register for signal `\sasc_top.\rxd_r2' using process `\sasc_top.$proc$rtl/sasc_top.v:251$94'. |
| created $dff cell `$procdff$344' with positive edge clock. |
| Creating register for signal `\sasc_top.\change' using process `\sasc_top.$proc$rtl/sasc_top.v:254$95'. |
| created $dff cell `$procdff$345' with positive edge clock. |
| Creating register for signal `\sasc_top.\dpll_state' using process `\sasc_top.$proc$rtl/sasc_top.v:262$98'. |
| created $adff cell `$procdff$346' with positive edge clock and negative level reset. |
| Creating register for signal `\sasc_top.\dpll_next_state' using process `\sasc_top.$proc$rtl/sasc_top.v:267$100'. |
| created direct connection (no actual register cell created). |
| Creating register for signal `\sasc_top.\rx_sio_ce_d' using process `\sasc_top.$proc$rtl/sasc_top.v:267$100'. |
| created direct connection (no actual register cell created). |
| Creating register for signal `\sasc_top.\rx_sio_ce_r1' using process `\sasc_top.$proc$rtl/sasc_top.v:290$101'. |
| created $dff cell `$procdff$347' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_sio_ce_r2' using process `\sasc_top.$proc$rtl/sasc_top.v:293$102'. |
| created $dff cell `$procdff$348' with positive edge clock. |
| Creating register for signal `\sasc_top.\rx_sio_ce' using process `\sasc_top.$proc$rtl/sasc_top.v:296$103'. |
| created $dff cell `$procdff$349' with positive edge clock. |
| |
| 6.6. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 3 empty switches in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:103$32'. |
| Removing empty process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:103$32'. |
| Found and cleaned up 1 empty switch in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| Removing empty process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:116$36'. |
| Found and cleaned up 4 empty switches in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:124$42'. |
| Removing empty process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:124$42'. |
| Found and cleaned up 3 empty switches in `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:93$28'. |
| Removing empty process `\sasc_fifo4.$proc$rtl/sasc_fifo4.v:93$28'. |
| Found and cleaned up 2 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:163$47'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:163$47'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:168$49'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:171$55'. |
| Found and cleaned up 2 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:176$57'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:176$57'. |
| Found and cleaned up 3 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:181$59'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:181$59'. |
| Found and cleaned up 3 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:188$62'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:188$62'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:195$66'. |
| Found and cleaned up 2 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:198$68'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:198$68'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:208$70'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:211$71'. |
| Found and cleaned up 3 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:216$75'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:216$75'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:223$81'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:226$83'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:229$85'. |
| Found and cleaned up 1 empty switch in `\sasc_top.$proc$rtl/sasc_top.v:234$90'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:234$90'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:237$92'. |
| Found and cleaned up 1 empty switch in `\sasc_top.$proc$rtl/sasc_top.v:248$93'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:248$93'. |
| Found and cleaned up 1 empty switch in `\sasc_top.$proc$rtl/sasc_top.v:251$94'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:251$94'. |
| Found and cleaned up 3 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:254$95'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:254$95'. |
| Found and cleaned up 2 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:262$98'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:262$98'. |
| Found and cleaned up 5 empty switches in `\sasc_top.$proc$rtl/sasc_top.v:267$100'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:267$100'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:290$101'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:293$102'. |
| Removing empty process `\sasc_top.$proc$rtl/sasc_top.v:296$103'. |
| Cleaned up 39 empty switches. |
| |
| 7. Executing OPT pass (performing simple optimizations). |
| |
| 7.1. Optimizing in-memory representation of design. |
| |
| 7.2. Executing OPT_CONST pass (perform const folding). |
| Replacing $eq cell `$eq$rtl/sasc_top.v:214$72' (1) in module `\sasc_top' with constant driver `$eq$rtl/sasc_top.v:214$72_Y = \rxd_r'. |
| |
| 7.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\sasc_fifo4'. |
| Cell `$eq$rtl/sasc_fifo4.v:121$40' is identical to cell `$eq$rtl/sasc_fifo4.v:120$37'. |
| Redirecting output \Y: $eq$rtl/sasc_fifo4.v:121$40_Y = $eq$rtl/sasc_fifo4.v:120$37_Y |
| Removing $eq cell `$eq$rtl/sasc_fifo4.v:121$40' from module `\sasc_fifo4'. |
| Cell `$logic_not$rtl/sasc_fifo4.v:125$43' is identical to cell `$logic_not$rtl/sasc_fifo4.v:104$33'. |
| Redirecting output \Y: $logic_not$rtl/sasc_fifo4.v:125$43_Y = $logic_not$rtl/sasc_fifo4.v:104$33_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_fifo4.v:125$43' from module `\sasc_fifo4'. |
| Cell `$logic_not$rtl/sasc_fifo4.v:94$29' is identical to cell `$logic_not$rtl/sasc_fifo4.v:104$33'. |
| Redirecting output \Y: $logic_not$rtl/sasc_fifo4.v:94$29_Y = $logic_not$rtl/sasc_fifo4.v:104$33_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_fifo4.v:94$29' from module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Cell `$and$rtl/sasc_top.v:193$64' is identical to cell `$and$rtl/sasc_top.v:179$58'. |
| Redirecting output \Y: $and$rtl/sasc_top.v:193$64_Y = $and$rtl/sasc_top.v:179$58_Y |
| Removing $and cell `$and$rtl/sasc_top.v:193$64' from module `\sasc_top'. |
| Cell `$and$rtl/sasc_top.v:235$91' is identical to cell `$and$rtl/sasc_top.v:221$79'. |
| Redirecting output \Y: $and$rtl/sasc_top.v:235$91_Y = $and$rtl/sasc_top.v:221$79_Y |
| Removing $and cell `$and$rtl/sasc_top.v:235$91' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:182$60' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:182$60_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:182$60' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:189$63' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:189$63_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:189$63' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:199$69' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:199$69_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:199$69' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:217$76' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:217$76_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:217$76' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:255$96' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:255$96_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:255$96' from module `\sasc_top'. |
| Cell `$logic_not$rtl/sasc_top.v:263$99' is identical to cell `$logic_not$rtl/sasc_top.v:164$48'. |
| Redirecting output \Y: $logic_not$rtl/sasc_top.v:263$99_Y = $logic_not$rtl/sasc_top.v:164$48_Y |
| Removing $logic_not cell `$logic_not$rtl/sasc_top.v:263$99' from module `\sasc_top'. |
| Cell `$procmux$256_CMP0' is identical to cell `$procmux$241_CMP0'. |
| Redirecting output \Y: $procmux$256_CMP = $procmux$241_CMP |
| Removing $eq cell `$procmux$256_CMP0' from module `\sasc_top'. |
| Cell `$procmux$260_CMP0' is identical to cell `$procmux$245_CMP0'. |
| Redirecting output \Y: $procmux$260_CMP = $procmux$245_CMP |
| Removing $eq cell `$procmux$260_CMP0' from module `\sasc_top'. |
| Cell `$procmux$274_CMP0' is identical to cell `$procmux$245_CMP0'. |
| Redirecting output \Y: $procmux$274_CMP = $procmux$245_CMP |
| Removing $eq cell `$procmux$274_CMP0' from module `\sasc_top'. |
| Cell `$procmux$285_CMP0' is identical to cell `$procmux$241_CMP0'. |
| Redirecting output \Y: $procmux$285_CMP = $procmux$241_CMP |
| Removing $eq cell `$procmux$285_CMP0' from module `\sasc_top'. |
| Cell `$procmux$289_CMP0' is identical to cell `$procmux$245_CMP0'. |
| Redirecting output \Y: $procmux$289_CMP = $procmux$245_CMP |
| Removing $eq cell `$procmux$289_CMP0' from module `\sasc_top'. |
| Cell `$procmux$297_CMP0' is identical to cell `$procmux$252_CMP0'. |
| Redirecting output \Y: $procmux$297_CMP = $procmux$252_CMP |
| Removing $eq cell `$procmux$297_CMP0' from module `\sasc_top'. |
| Cell `$procmux$301_CMP0' is identical to cell `$procmux$241_CMP0'. |
| Redirecting output \Y: $procmux$301_CMP = $procmux$241_CMP |
| Removing $eq cell `$procmux$301_CMP0' from module `\sasc_top'. |
| Cell `$procmux$305_CMP0' is identical to cell `$procmux$245_CMP0'. |
| Redirecting output \Y: $procmux$305_CMP = $procmux$245_CMP |
| Removing $eq cell `$procmux$305_CMP0' from module `\sasc_top'. |
| Cell `$procmux$312_CMP0' is identical to cell `$procmux$252_CMP0'. |
| Redirecting output \Y: $procmux$312_CMP = $procmux$252_CMP |
| Removing $eq cell `$procmux$312_CMP0' from module `\sasc_top'. |
| Cell `$procmux$316_CMP0' is identical to cell `$procmux$241_CMP0'. |
| Redirecting output \Y: $procmux$316_CMP = $procmux$241_CMP |
| Removing $eq cell `$procmux$316_CMP0' from module `\sasc_top'. |
| Cell `$procmux$320_CMP0' is identical to cell `$procmux$245_CMP0'. |
| Redirecting output \Y: $procmux$320_CMP = $procmux$245_CMP |
| Removing $eq cell `$procmux$320_CMP0' from module `\sasc_top'. |
| Removed a total of 22 cells. |
| |
| 7.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| dead port 2/2 on $mux $procmux$273. |
| dead port 2/3 on $pmux $procmux$284. |
| dead port 3/3 on $pmux $procmux$284. |
| dead port 2/4 on $pmux $procmux$296. |
| dead port 3/4 on $pmux $procmux$296. |
| dead port 4/4 on $pmux $procmux$296. |
| dead port 1/4 on $pmux $procmux$311. |
| dead port 2/4 on $pmux $procmux$311. |
| dead port 3/4 on $pmux $procmux$311. |
| Removed 9 multiplexer ports. |
| |
| 7.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| New ctrl vector for $pmux cell $procmux$240: $procmux$241_CMP |
| Performed a total of 1 changes. |
| |
| 7.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 7.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 7.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| removing unused `$add' cell `$add$rtl/sasc_fifo4.v:101$31'. |
| removing unused non-port wire \wp_p2. |
| removed 27 unused temporary wires. |
| Finding unused cells or wires in module \sasc_top.. |
| removing unused `$mux' cell `$procmux$193'. |
| removing unused `$dff' cell `$procdff$329'. |
| removing unused `$dff' cell `$procdff$343'. |
| removing unused `$dff' cell `$procdff$344'. |
| removing unused `$mux' cell `$procmux$190'. |
| removing unused non-port wire \load_r. |
| removing unused non-port wire \lock_en. |
| removing unused non-port wire \rxd_r1. |
| removing unused non-port wire \rxd_r2. |
| removed 91 unused temporary wires. |
| |
| 7.9. Executing OPT_CONST pass (perform const folding). |
| |
| 7.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 7.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 7.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 7.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 7.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 7.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| Finding unused cells or wires in module \sasc_top.. |
| |
| 7.16. Executing OPT_CONST pass (perform const folding). |
| |
| 7.17. Optimizing in-memory representation of design. |
| |
| 7.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 8. Executing MEMORY pass. |
| |
| 8.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| Checking cell `$memwr$\mem$rtl/sasc_fifo4.v:117$46' in module `\sasc_fifo4': merged $dff to cell. |
| |
| 8.2. Executing MEMORY_COLLECT pass (generating $mem cells). |
| Collecting $memrd and $memwr for memory `\mem' in module `\sasc_fifo4': |
| |
| 8.3. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| Mapping memory cell $mem$\mem$350 in module \sasc_fifo4: |
| created 4 $dff cells and 0 static cells of width 8. |
| read interface: 0 $dff and 3 $mux cells. |
| write interface: 4 blocks of $eq, $and and $mux cells. |
| |
| 9. Executing OPT pass (performing simple optimizations). |
| |
| 9.1. Optimizing in-memory representation of design. |
| |
| 9.2. Executing OPT_CONST pass (perform const folding). |
| |
| 9.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 9.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 9.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 9.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 9.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 9.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| removing unused `$dff' cell `$procdff$323'. |
| removing unused `$dff' cell `$procdff$324'. |
| removing unused `$dff' cell `$procdff$322'. |
| removed 11 unused temporary wires. |
| Finding unused cells or wires in module \sasc_top.. |
| |
| 9.9. Executing OPT_CONST pass (perform const folding). |
| |
| 9.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 9.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| |
| 9.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 9.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 9.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 9.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| Finding unused cells or wires in module \sasc_top.. |
| |
| 9.16. Executing OPT_CONST pass (perform const folding). |
| |
| 9.17. Optimizing in-memory representation of design. |
| |
| 9.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 10. Executing TECHMAP pass (map to technology primitives). |
| |
| 10.1. Executing Verilog-2005 frontend. |
| Full command line: read_verilog <stdcells.v> |
| Parsing Verilog input from `<stdcells.v>' to AST representation. |
| Generating RTLIL representation for module `\$not'. |
| Generating RTLIL representation for module `\$pos'. |
| Generating RTLIL representation for module `\$neg'. |
| Generating RTLIL representation for module `\$and'. |
| Generating RTLIL representation for module `\$or'. |
| Generating RTLIL representation for module `\$xor'. |
| Generating RTLIL representation for module `\$xnor'. |
| Generating RTLIL representation for module `\$reduce_and'. |
| Generating RTLIL representation for module `\$reduce_or'. |
| Generating RTLIL representation for module `\$reduce_xor'. |
| Generating RTLIL representation for module `\$reduce_xnor'. |
| Generating RTLIL representation for module `\$reduce_bool'. |
| Generating RTLIL representation for module `\$shift'. |
| Generating RTLIL representation for module `\$shl'. |
| Generating RTLIL representation for module `\$shr'. |
| Generating RTLIL representation for module `\$sshl'. |
| Generating RTLIL representation for module `\$sshr'. |
| Generating RTLIL representation for module `\$fulladd'. |
| Generating RTLIL representation for module `\$alu'. |
| Generating RTLIL representation for module `\$lt'. |
| Generating RTLIL representation for module `\$le'. |
| Generating RTLIL representation for module `\$eq'. |
| Generating RTLIL representation for module `\$ne'. |
| Generating RTLIL representation for module `\$ge'. |
| Generating RTLIL representation for module `\$gt'. |
| Generating RTLIL representation for module `\$add'. |
| Generating RTLIL representation for module `\$sub'. |
| Generating RTLIL representation for module `\$logic_not'. |
| Generating RTLIL representation for module `\$logic_and'. |
| Generating RTLIL representation for module `\$logic_or'. |
| Generating RTLIL representation for module `\$mux'. |
| Generating RTLIL representation for module `\$pmux'. |
| Generating RTLIL representation for module `\$safe_pmux'. |
| Generating RTLIL representation for module `\$dff'. |
| Generating RTLIL representation for module `\$adff'. |
| Successfully finished Verilog frontend. |
| |
| 10.2. Executing AST frontend in derive mode using pre-parsed AST for module `$add'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.3. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.4. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.5. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:120$39' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:121$41' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:129$45' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.6. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.7. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:120$37' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:129$44' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.8. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.9. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$logic_not$rtl/sasc_fifo4.v:104$33' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$logic_not$rtl/sasc_fifo4.v:120$38' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.10. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 8 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=8'. |
| |
| 10.11. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$rdmux[0][0][0]$359' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$rdmux[0][1][0]$362' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$rdmux[0][1][1]$365' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[0][0]$370' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[1][0]$376' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[2][0]$382' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[3][0]$388' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[0][0]$368' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[1][0]$374' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[2][0]$380' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[3][0]$386' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wrmux[0][0]$372' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wrmux[1][0]$378' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wrmux[2][0]$384' using `$paramod$mux\WIDTH=8'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wrmux[3][0]$390' using `$paramod$mux\WIDTH=8'. |
| |
| 10.12. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 8 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 10.13. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350[0]$351' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350[1]$353' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350[2]$355' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350[3]$357' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'. |
| |
| 10.14. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 2 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 2'00 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 10.15. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$procdff$321' using `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 10.16. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 1 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.17. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$procdff$325' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_fifo4.$procdff$326' using `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'00'. |
| |
| 10.18. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=2'. |
| |
| 10.19. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$procmux$107' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_fifo4.$procmux$110' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_fifo4.$procmux$114' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_fifo4.$procmux$117' using `$paramod$mux\WIDTH=8'. |
| |
| 10.20. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=1'. |
| |
| 10.21. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$procmux$120' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_fifo4.$procmux$123' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_fifo4.$procmux$126' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_fifo4.$procmux$129' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_fifo4.$procmux$132' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_fifo4.$procmux$135' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_fifo4.$procmux$138' using `$paramod$mux\WIDTH=2'. |
| |
| 10.22. Executing AST frontend in derive mode using pre-parsed AST for module `$add'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.23. Continuing TECHMAP pass. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$52' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$54' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:174$56' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:179$58' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:214$74' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:219$78' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:221$79' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$87' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$89' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:297$105' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.24. Executing AST frontend in derive mode using pre-parsed AST for module `$not'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.25. Continuing TECHMAP pass. |
| Mapping `sasc_top.$eq$rtl/sasc_top.v:214$73' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.26. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.27. Continuing TECHMAP pass. |
| Mapping `sasc_top.$eq$rtl/sasc_top.v:227$84' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:164$48' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$50' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$51' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$53' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:219$77' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:232$86' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:232$88' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:297$104' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.28. Executing AST frontend in derive mode using pre-parsed AST for module `$ne'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.29. Continuing TECHMAP pass. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:196$67' using `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:224$82' using `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.30. Executing AST frontend in derive mode using pre-parsed AST for module `$ne'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.31. Continuing TECHMAP pass. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:257$97' using `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.32. Executing AST frontend in derive mode using pre-parsed AST for module `$or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.33. Continuing TECHMAP pass. |
| Mapping `sasc_top.$or$rtl/sasc_top.v:185$61' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$procdff$327' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$328' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.34. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 10 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=10\CLK_POLARITY=1'1'. |
| |
| 10.35. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procdff$330' using `$paramod$dff\WIDTH=10\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$331' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.36. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'. |
| Parameter \WIDTH = 4 |
| Parameter \CLK_POLARITY = 1'1 |
| Generating RTLIL representation for module `$paramod$dff\WIDTH=4\CLK_POLARITY=1'1'. |
| |
| 10.37. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procdff$332' using `$paramod$dff\WIDTH=4\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$333' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$334' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$335' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$336' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$337' using `$paramod$dff\WIDTH=4\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$338' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$339' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$340' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$341' using `$paramod$dff\WIDTH=10\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$342' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$345' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| |
| 10.38. Executing AST frontend in derive mode using pre-parsed AST for module `$adff'. |
| Parameter \WIDTH = 2 |
| Parameter \CLK_POLARITY = 1'1 |
| Parameter \ARST_POLARITY = 1'0 |
| Parameter \ARST_VALUE = 2'01 |
| Generating RTLIL representation for module `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'01'. |
| |
| 10.39. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procdff$346' using `$paramod$adff\WIDTH=2\CLK_POLARITY=1'1\ARST_POLARITY=1'0\ARST_VALUE=2'01'. |
| Mapping `sasc_top.$procdff$347' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$348' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procdff$349' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'. |
| Mapping `sasc_top.$procmux$142' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$145' using `$paramod$mux\WIDTH=1'. |
| |
| 10.40. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 10 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=10'. |
| |
| 10.41. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procmux$148' using `$paramod$mux\WIDTH=10'. |
| Mapping `sasc_top.$procmux$151' using `$paramod$mux\WIDTH=10'. |
| Mapping `sasc_top.$procmux$155' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$157' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$160' using `$paramod$mux\WIDTH=1'. |
| |
| 10.42. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'. |
| Parameter \WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$mux\WIDTH=4'. |
| |
| 10.43. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procmux$163' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$166' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$169' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$172' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$175' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$178' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$181' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$184' using `$paramod$mux\WIDTH=4'. |
| Mapping `sasc_top.$procmux$187' using `$paramod$mux\WIDTH=10'. |
| Mapping `sasc_top.$procmux$196' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$199' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$202' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$205' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_top.$procmux$240' using `$paramod$mux\WIDTH=1'. |
| Mapping `sasc_top.$procmux$241_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_top.$procmux$245_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.44. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'. |
| Parameter \WIDTH = 2 |
| Parameter \S_WIDTH = 3 |
| Generating RTLIL representation for module `$paramod$pmux\WIDTH=2\S_WIDTH=3'. |
| |
| 10.45. Continuing TECHMAP pass. |
| Mapping `sasc_top.$procmux$251' using `$paramod$pmux\WIDTH=2\S_WIDTH=3'. |
| Mapping `sasc_top.$procmux$252_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_top.$procmux$271' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_top.$procmux$282' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_top.$procmux$294' using `$paramod$mux\WIDTH=2'. |
| |
| 10.46. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.47. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.48. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=2'. |
| |
| 10.49. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30.alu' using `$paramod$alu\WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34.alu' using `$paramod$alu\WIDTH=2'. |
| |
| 10.50. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.51. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:120$39.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:120$39.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:121$41.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:121$41.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:129$45.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$and$rtl/sasc_fifo4.v:129$45.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:120$37.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:120$37.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:129$44.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$eq$rtl/sasc_fifo4.v:129$44.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.52. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_bool'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| |
| 10.53. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$logic_not$rtl/sasc_fifo4.v:104$33.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_fifo4.$logic_not$rtl/sasc_fifo4.v:120$38.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[0][0]$370.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[0][0]$370.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[1][0]$376.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[1][0]$376.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[2][0]$382.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[2][0]$382.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[3][0]$388.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wren[3][0]$388.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[0][0]$368.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[0][0]$368.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[1][0]$374.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[1][0]$374.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[2][0]$380.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[2][0]$380.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[3][0]$386.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$memory$mem$\mem$350$wreq[3][0]$386.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:120$37.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.54. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.55. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:120$37.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| |
| 10.56. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.57. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:120$37.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:129$44.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:129$44.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:129$44.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[0][0]$368.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[0][0]$368.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[1][0]$374.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[1][0]$374.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[2][0]$380.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[2][0]$380.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[3][0]$386.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[3][0]$386.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.58. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.59. Continuing TECHMAP pass. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.60. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'. |
| Parameter \WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$alu\WIDTH=4'. |
| |
| 10.61. Continuing TECHMAP pass. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.alu' using `$paramod$alu\WIDTH=4'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.alu' using `$paramod$alu\WIDTH=4'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$52.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$52.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$54.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:169$54.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:174$56.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:174$56.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:179$58.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:179$58.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:214$74.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:214$74.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:219$78.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:219$78.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:221$79.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:221$79.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$87.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$87.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$89.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:232$89.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:297$105.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$and$rtl/sasc_top.v:297$105.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$eq$rtl/sasc_top.v:227$84.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$eq$rtl/sasc_top.v:227$84.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:164$48.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$50.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$51.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:169$53.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:219$77.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:232$86.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:232$88.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$logic_not$rtl/sasc_top.v:297$104.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:196$67.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:196$67.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:224$82.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:224$82.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.62. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 1'0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.63. Continuing TECHMAP pass. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:257$97.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$ne$rtl/sasc_top.v:257$97.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$or$rtl/sasc_top.v:185$61.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$or$rtl/sasc_top.v:185$61.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$procmux$241_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$procmux$241_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$procmux$245_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$procmux$245_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$procmux$252_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$procmux$252_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$eq$rtl/sasc_top.v:227$84.$not$<stdcells.v>:808$424' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.64. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.65. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$eq$rtl/sasc_top.v:227$84.$reduce_or$<stdcells.v>:808$423' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| |
| 10.66. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \B_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.67. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:196$67.$reduce_or$<stdcells.v>:833$426' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:224$82.$reduce_or$<stdcells.v>:833$426' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.68. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.69. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:257$97.$reduce_or$<stdcells.v>:833$428' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.70. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 1 |
| Parameter \B_WIDTH = 1 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| |
| 10.71. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:257$97.$xor$<stdcells.v>:833$427' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$241_CMP0.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$241_CMP0.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$241_CMP0.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$245_CMP0.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$245_CMP0.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.72. Executing AST frontend in derive mode using pre-parsed AST for module `$and'. |
| Parameter \A_SIGNED = 0 |
| Parameter \B_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \B_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.73. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$431' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$432' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$433' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.74. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 3 |
| Parameter \Y_WIDTH = 1 |
| Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| |
| 10.75. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$procmux$251.$reduce_or$<stdcells.v>:1210$434' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$251.$reduce_or$<stdcells.v>:1210$435' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$251.$reduce_or$<stdcells.v>:1214$429' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$251.$ternary$<stdcells.v>:1214$430' using `$paramod$mux\WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$252_CMP0.$not$<stdcells.v>:808$421' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$252_CMP0.$reduce_or$<stdcells.v>:808$420' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$252_CMP0.$xor$<stdcells.v>:808$419' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder' using `$fulladd'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder' using `$fulladd'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder' using `$fulladd'. |
| Mapping `sasc_fifo4.$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder' using `$fulladd'. |
| |
| 10.76. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 2 |
| Parameter \Y_WIDTH = 2 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| |
| 10.77. Continuing TECHMAP pass. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:120$37.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:120$37.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:129$44.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$eq$rtl/sasc_fifo4.v:129$44.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_fifo4.$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.alu.V[0].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.alu.V[1].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.alu.V[2].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:193$65.alu.V[3].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.alu.V[0].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.alu.V[1].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.alu.V[2].adder' using `$fulladd'. |
| Mapping `sasc_top.$add$rtl/sasc_top.v:221$80.alu.V[3].adder' using `$fulladd'. |
| |
| 10.78. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'. |
| Parameter \A_SIGNED = 0 |
| Parameter \A_WIDTH = 4 |
| Parameter \Y_WIDTH = 4 |
| Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| |
| 10.79. Continuing TECHMAP pass. |
| Mapping `sasc_top.$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=4\Y_WIDTH=4'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:257$97.$xor$<stdcells.v>:833$427.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$ne$rtl/sasc_top.v:257$97.$xor$<stdcells.v>:833$427.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. |
| Mapping `sasc_top.$techmap$procmux$241_CMP0.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$241_CMP0.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$431.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$431.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$432.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$432.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$433.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$251.$and$<stdcells.v>:1203$433.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$252_CMP0.$xor$<stdcells.v>:808$419.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| Mapping `sasc_top.$techmap$procmux$252_CMP0.$xor$<stdcells.v>:808$419.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'. |
| No more expansions possible. |
| |
| 11. Executing OPT pass (performing simple optimizations). |
| |
| 11.1. Optimizing in-memory representation of design. |
| |
| 11.2. Executing OPT_CONST pass (perform const folding). |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.gate1' (?1) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.t1 = $procdff$326.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.gate3' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.gate4' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.Y = $add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.gate1' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.gate2' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.t2 = $procdff$326.Q [1]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.gate1' (?1) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.t1 = $procdff$321.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.gate3' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.gate4' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.Y = $add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.gate1' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.gate2' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.t2 = $procdff$321.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.V[0].gate' (0?) in module `\sasc_fifo4' with constant driver `$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.Y [0] = $procmux$114.Y [0]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.V[1].gate' (0?) in module `\sasc_fifo4' with constant driver `$techmap$memory$mem$\mem$350$wreq[0][0]$368.$xor$<stdcells.v>:808$419.Y [1] = $procmux$114.Y [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.V[1].gate' (0?) in module `\sasc_fifo4' with constant driver `$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.Y [1] = $procmux$114.Y [1]'. |
| Replacing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.V[0].gate' (0?) in module `\sasc_fifo4' with constant driver `$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.Y [0] = $procmux$114.Y [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.gate5' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[0].adder.X = $procdff$326.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.gate5' (0?) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.X = $add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.gate5' (?0) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[0].adder.X = $procdff$321.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.gate5' (0?) in module `\sasc_fifo4' with constant driver `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.X = $add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.t3'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.gate1' (?1) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.t1 = $procdff$332.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.gate3' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.gate4' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.Y = $add$rtl/sasc_top.v:193$65.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.t2 = $procdff$332.Q [1]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.t2 = $procdff$332.Q [2]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.t2 = $procdff$332.Q [3]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.gate1' (?1) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.t1 = $procdff$337.Q [0]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.gate3' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.t3 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.gate4' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.Y = $add$rtl/sasc_top.v:221$80.alu.V[0].adder.t2'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.t2 = $procdff$337.Q [1]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.t2 = $procdff$337.Q [2]'. |
| Replacing $_AND_ cell `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.gate1' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.t1 = 1'0'. |
| Replacing $_XOR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.gate2' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.t2 = $procdff$337.Q [3]'. |
| Replacing $_MUX_ cell `$procmux$271.V[1].gate' (00?) in module `\sasc_top' with constant driver `$procmux$271.Y [1] = 1'0'. |
| Replacing $_MUX_ cell `$procmux$282.V[1].gate' (11?) in module `\sasc_top' with constant driver `$procmux$282.Y [1] = 1'1'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.V[1].gate' (?0) in module `\sasc_top' with constant driver `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.Y [1] = $procdff$337.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.V[2].gate' (?0) in module `\sasc_top' with constant driver `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.Y [2] = $procdff$337.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.V[1].gate' (?0) in module `\sasc_top' with constant driver `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.Y [1] = $procdff$332.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.V[2].gate' (?0) in module `\sasc_top' with constant driver `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.Y [2] = $procdff$332.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.V[0].gate' (?0) in module `\sasc_top' with constant driver `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.Y [0] = $procdff$337.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.V[2].gate' (?0) in module `\sasc_top' with constant driver `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.Y [2] = $procdff$337.Q [2]'. |
| Replacing $_XOR_ cell `$techmap$procmux$241_CMP0.$xor$<stdcells.v>:808$419.V[1].gate' (?0) in module `\sasc_top' with constant driver `$techmap$procmux$241_CMP0.$xor$<stdcells.v>:808$419.Y [1] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.V[0].gate' (?0) in module `\sasc_top' with constant driver `$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.Y [0] = $procdff$346.Q [0]'. |
| Replacing $_XOR_ cell `$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.V[1].gate' (?0) in module `\sasc_top' with constant driver `$techmap$procmux$245_CMP0.$xor$<stdcells.v>:808$419.Y [1] = $procdff$346.Q [1]'. |
| Replacing $_XOR_ cell `$techmap$procmux$252_CMP0.$xor$<stdcells.v>:808$419.V[0].gate' (?0) in module `\sasc_top' with constant driver `$techmap$procmux$252_CMP0.$xor$<stdcells.v>:808$419.Y [0] = $procdff$346.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.gate5' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.X = $procdff$332.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[1].adder.X = $add$rtl/sasc_top.v:193$65.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[2].adder.X = $add$rtl/sasc_top.v:193$65.alu.V[2].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.X = $add$rtl/sasc_top.v:193$65.alu.V[3].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.gate5' (?0) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.X = $procdff$337.Q [0]'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[1].adder.X = $add$rtl/sasc_top.v:221$80.alu.V[1].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[2].adder.X = $add$rtl/sasc_top.v:221$80.alu.V[2].adder.t3'. |
| Replacing $_OR_ cell `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.gate5' (0?) in module `\sasc_top' with constant driver `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.X = $add$rtl/sasc_top.v:221$80.alu.V[3].adder.t3'. |
| Replacing $_AND_ cell `$techmap$procmux$251.$and$<stdcells.v>:1203$432.V[1].gate' (1?) in module `\sasc_top' with constant driver `$techmap$procmux$251.$and$<stdcells.v>:1203$432.Y [1] = $techmap$procmux$241_CMP0.$not$<stdcells.v>:808$421.Y'. |
| Replacing $_AND_ cell `$techmap$procmux$251.$and$<stdcells.v>:1203$433.V[1].gate' (0?) in module `\sasc_top' with constant driver `$techmap$procmux$251.$and$<stdcells.v>:1203$433.Y [1] = 1'0'. |
| Replacing $_OR_ cell `$techmap$procmux$251.$reduce_or$<stdcells.v>:1210$435.V[2].gate' (0?) in module `\sasc_top' with constant driver `$techmap$procmux$251.$reduce_or$<stdcells.v>:1210$435.buffer [2] = $techmap$procmux$251.$reduce_or$<stdcells.v>:1210$435.buffer [1]'. |
| |
| 11.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\sasc_fifo4'. |
| Cell `$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.V[0].gate' is identical to cell `$techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.V[0].gate'. |
| Redirecting output \Y: $techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.Y [0] = $techmap$memory$mem$\mem$350$wreq[1][0]$374.$xor$<stdcells.v>:808$419.Y [0] |
| Removing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.V[0].gate' from module `\sasc_fifo4'. |
| Cell `$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.V[1].gate' is identical to cell `$techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.V[1].gate'. |
| Redirecting output \Y: $techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.Y [1] = $techmap$memory$mem$\mem$350$wreq[2][0]$380.$xor$<stdcells.v>:808$419.Y [1] |
| Removing $_XOR_ cell `$techmap$memory$mem$\mem$350$wreq[3][0]$386.$xor$<stdcells.v>:808$419.V[1].gate' from module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Cell `$procmux$294.V[0].gate' is identical to cell `$procmux$271.V[0].gate'. |
| Redirecting output \Y: $procmux$294.Y [0] = $procmux$271.Y [0] |
| Removing $_MUX_ cell `$procmux$294.V[0].gate' from module `\sasc_top'. |
| Cell `$procmux$294.V[1].gate' is identical to cell `$procmux$271.V[0].gate'. |
| Redirecting output \Y: $procmux$294.Y [1] = $procmux$271.Y [0] |
| Removing $_MUX_ cell `$procmux$294.V[1].gate' from module `\sasc_top'. |
| Cell `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.V[0].gate' is identical to cell `$add$rtl/sasc_top.v:221$80.alu.V[0].adder.gate2'. |
| Redirecting output \Y: $techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.Y [0] = $add$rtl/sasc_top.v:221$80.alu.V[0].adder.t2 |
| Removing $_XOR_ cell `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.V[0].gate' from module `\sasc_top'. |
| Cell `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.V[0].gate' is identical to cell `$add$rtl/sasc_top.v:193$65.alu.V[0].adder.gate2'. |
| Redirecting output \Y: $techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.Y [0] = $add$rtl/sasc_top.v:193$65.alu.V[0].adder.t2 |
| Removing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:196$67.$xor$<stdcells.v>:833$425.V[0].gate' from module `\sasc_top'. |
| Cell `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.V[3].gate' is identical to cell `$techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.V[3].gate'. |
| Redirecting output \Y: $techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.Y [3] = $techmap$eq$rtl/sasc_top.v:227$84.$xor$<stdcells.v>:808$422.Y [3] |
| Removing $_XOR_ cell `$techmap$ne$rtl/sasc_top.v:224$82.$xor$<stdcells.v>:833$425.V[3].gate' from module `\sasc_top'. |
| Cell `$techmap$procmux$251.$and$<stdcells.v>:1203$431.V[1].gate' is identical to cell `$techmap$procmux$251.$and$<stdcells.v>:1203$431.V[0].gate'. |
| Redirecting output \Y: $techmap$procmux$251.$and$<stdcells.v>:1203$431.Y [1] = $techmap$procmux$251.$and$<stdcells.v>:1203$431.Y [0] |
| Removing $_AND_ cell `$techmap$procmux$251.$and$<stdcells.v>:1203$431.V[1].gate' from module `\sasc_top'. |
| Removed a total of 8 cells. |
| |
| 11.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 11.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 11.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 11.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| removing unused `$_AND_' cell `$add$rtl/sasc_fifo4.v:100$30.alu.V[1].adder.gate3'. |
| removing unused `$_AND_' cell `$add$rtl/sasc_fifo4.v:110$34.alu.V[1].adder.gate3'. |
| removed 398 unused temporary wires. |
| Finding unused cells or wires in module \sasc_top.. |
| removing unused `$_DFF_P_' cell `$procdff$341.V[0].ff'. |
| removing unused `$_MUX_' cell `$procmux$187.V[0].gate'. |
| removing unused `$_DFF_P_' cell `$procdff$341.V[1].ff'. |
| removing unused `$_MUX_' cell `$procmux$187.V[1].gate'. |
| removing unused `$_AND_' cell `$add$rtl/sasc_top.v:193$65.alu.V[3].adder.gate3'. |
| removing unused `$_AND_' cell `$add$rtl/sasc_top.v:221$80.alu.V[3].adder.gate3'. |
| removed 631 unused temporary wires. |
| |
| 11.9. Executing OPT_CONST pass (perform const folding). |
| |
| 11.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 11.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 11.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 11.13. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 11.14. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 11.15. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| Finding unused cells or wires in module \sasc_top.. |
| |
| 11.16. Executing OPT_CONST pass (perform const folding). |
| |
| 11.17. Optimizing in-memory representation of design. |
| |
| 11.18. Finished OPT passes. (There is nothing left to do.) |
| |
| 12. Executing ABC pass (technology mapping using ABC). |
| |
| 12.1. Extracting gate logic of module `\sasc_fifo4' to `/tmp/yosys-abc-Wavd1W/input.v'.. |
| Extracted 110 gates and 162 wires to a logic network with 49 inputs and 47 outputs. |
| |
| 12.1.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-Wavd1W/input.v; read_library /tmp/yosys-abc-Wavd1W/stdcells.genlib; map; write_verilog /tmp/yosys-abc-Wavd1W/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-Wavd1W/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-Wavd1W/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-Wavd1W/stdcells.super". Time = 0.00 sec |
| |
| 12.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 25 |
| ABC RESULTS: INV cells: 10 |
| ABC RESULTS: MUX cells: 58 |
| ABC RESULTS: OR cells: 9 |
| ABC RESULTS: XOR cells: 6 |
| ABC RESULTS: internal signals: 66 |
| ABC RESULTS: input signals: 49 |
| ABC RESULTS: output signals: 47 |
| |
| 12.1.3. Removing temp directory `/tmp/yosys-abc-Wavd1W': |
| Removing `/tmp/yosys-abc-Wavd1W/input.v'. |
| Removing `/tmp/yosys-abc-Wavd1W/output.v'. |
| Removing `/tmp/yosys-abc-Wavd1W/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-Wavd1W/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-Wavd1W/stdcells.super'. |
| Removing `/tmp/yosys-abc-Wavd1W'. |
| |
| 12.2. Extracting gate logic of module `\sasc_top' to `/tmp/yosys-abc-miZI4W/input.v'.. |
| Extracted 131 gates and 189 wires to a logic network with 56 inputs and 40 outputs. |
| |
| 12.2.1. Executing ABC. |
| ABC: ABC command line: "read_verilog /tmp/yosys-abc-miZI4W/input.v; read_library /tmp/yosys-abc-miZI4W/stdcells.genlib; map; write_verilog /tmp/yosys-abc-miZI4W/output.v". |
| ABC: There is no hierarchy information. |
| ABC: The number of gates read = 8. |
| ABC: Read 8 gates from file "/tmp/yosys-abc-miZI4W/stdcells.genlib". |
| ABC: Selected 8 functionally unique gates. Time = 0.00 sec |
| ABC: Created 4 rules and 4 matches. Time = 0.00 sec |
| ABC: Warning: The network was strashed and balanced before mapping. |
| ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-miZI4W/stdcells.genlib". |
| ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-miZI4W/stdcells.super". Time = 0.00 sec |
| |
| 12.2.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 39 |
| ABC RESULTS: INV cells: 21 |
| ABC RESULTS: MUX cells: 35 |
| ABC RESULTS: OR cells: 22 |
| ABC RESULTS: XOR cells: 9 |
| ABC RESULTS: internal signals: 93 |
| ABC RESULTS: input signals: 56 |
| ABC RESULTS: output signals: 40 |
| |
| 12.2.3. Removing temp directory `/tmp/yosys-abc-miZI4W': |
| Removing `/tmp/yosys-abc-miZI4W/input.v'. |
| Removing `/tmp/yosys-abc-miZI4W/output.v'. |
| Removing `/tmp/yosys-abc-miZI4W/stdcells.genlib'. |
| Removing `/tmp/yosys-abc-miZI4W/stdcells.genlib_temp'. |
| Removing `/tmp/yosys-abc-miZI4W/stdcells.super'. |
| Removing `/tmp/yosys-abc-miZI4W'. |
| |
| 13. Executing OPT pass (performing simple optimizations). |
| |
| 13.1. Optimizing in-memory representation of design. |
| |
| 13.2. Executing OPT_CONST pass (perform const folding). |
| |
| 13.3. Executing OPT_SHARE pass (detect identical cells). |
| Full command line: opt_share -nomux |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 13.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizier on module \sasc_fifo4.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizier on module \sasc_top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 13.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \sasc_fifo4. |
| Optimizing cells in module \sasc_top. |
| Performed a total of 0 changes. |
| |
| 13.6. Executing OPT_SHARE pass (detect identical cells). |
| Finding identical cells in module `\sasc_fifo4'. |
| Finding identical cells in module `\sasc_top'. |
| Removed a total of 0 cells. |
| |
| 13.7. Executing OPT_RMDFF pass (remove dff with constant values). |
| Replaced 0 DFF cells. |
| |
| 13.8. Executing OPT_RMUNUSED pass (remove unused cells and wires). |
| Finding unused cells or wires in module \sasc_fifo4.. |
| removing unused non-port wire \rp_p1. |
| removing unused non-port wire \wp_p1. |
| removed 131 unused temporary wires. |
| Finding unused cells or wires in module \sasc_top.. |
| removing unused non-port wire \dpll_next_state. |
| removing unused non-port wire \start. |
| removed 153 unused temporary wires. |
| |
| 13.9. Executing OPT_CONST pass (perform const folding). |
| |
| 13.10. Optimizing in-memory representation of design. |
| |
| 13.11. Finished OPT passes. (There is nothing left to do.) |
| |
| 14. Executing Verilog backend. |
| Full command line: write_verilog -noattr output/synth.v |
| Dumping module `\sasc_fifo4'. |
| renaming `$0\gb[0:0]' to `_000_'. |
| renaming `$0\rp[1:0]' to `_001_'. |
| renaming `$0\wp[1:0]' to `_002_'. |
| renaming `$abc$436$g000' to `_068_'. |
| renaming `$abc$436$g001' to `_069_'. |
| renaming `$abc$436$g002' to `_070_'. |
| renaming `$abc$436$g003' to `_071_'. |
| renaming `$abc$436$g004' to `_072_'. |
| renaming `$abc$436$g005' to `_073_'. |
| renaming `$abc$436$g006' to `_074_'. |
| renaming `$abc$436$g007' to `_075_'. |
| renaming `$abc$436$g008' to `_076_'. |
| renaming `$abc$436$g009' to `_077_'. |
| renaming `$abc$436$g010' to `_078_'. |
| renaming `$abc$436$g011' to `_079_'. |
| renaming `$abc$436$g012' to `_080_'. |
| renaming `$abc$436$g013' to `_081_'. |
| renaming `$abc$436$g014' to `_082_'. |
| renaming `$abc$436$g015' to `_083_'. |
| renaming `$abc$436$g016' to `_084_'. |
| renaming `$abc$436$g017' to `_085_'. |
| renaming `$abc$436$g018' to `_086_'. |
| renaming `$abc$436$g019' to `_087_'. |
| renaming `$abc$436$g020' to `_088_'. |
| renaming `$abc$436$g021' to `_089_'. |
| renaming `$abc$436$g022' to `_090_'. |
| renaming `$abc$436$g023' to `_091_'. |
| renaming `$abc$436$g024' to `_092_'. |
| renaming `$abc$436$g025' to `_093_'. |
| renaming `$abc$436$g026' to `_094_'. |
| renaming `$abc$436$g027' to `_095_'. |
| renaming `$abc$436$g028' to `_096_'. |
| renaming `$abc$436$g029' to `_097_'. |
| renaming `$abc$436$g030' to `_098_'. |
| renaming `$abc$436$g031' to `_099_'. |
| renaming `$abc$436$g032' to `_100_'. |
| renaming `$abc$436$g033' to `_101_'. |
| renaming `$abc$436$g034' to `_102_'. |
| renaming `$abc$436$g035' to `_103_'. |
| renaming `$abc$436$g036' to `_104_'. |
| renaming `$abc$436$g037' to `_105_'. |
| renaming `$abc$436$g038' to `_106_'. |
| renaming `$abc$436$g039' to `_107_'. |
| renaming `$abc$436$g040' to `_108_'. |
| renaming `$abc$436$g041' to `_109_'. |
| renaming `$abc$436$g042' to `_110_'. |
| renaming `$abc$436$g043' to `_111_'. |
| renaming `$abc$436$g044' to `_112_'. |
| renaming `$abc$436$g045' to `_113_'. |
| renaming `$abc$436$g046' to `_114_'. |
| renaming `$abc$436$g047' to `_115_'. |
| renaming `$abc$436$g048' to `_116_'. |
| renaming `$abc$436$g049' to `_117_'. |
| renaming `$abc$436$g050' to `_118_'. |
| renaming `$abc$436$g051' to `_119_'. |
| renaming `$abc$436$g052' to `_120_'. |
| renaming `$abc$436$g053' to `_121_'. |
| renaming `$abc$436$g054' to `_122_'. |
| renaming `$abc$436$g055' to `_123_'. |
| renaming `$abc$436$g056' to `_124_'. |
| renaming `$abc$436$g057' to `_125_'. |
| renaming `$abc$436$g058' to `_126_'. |
| renaming `$abc$436$g059' to `_127_'. |
| renaming `$abc$436$g060' to `_128_'. |
| renaming `$abc$436$g061' to `_129_'. |
| renaming `$abc$436$g062' to `_130_'. |
| renaming `$abc$436$g063' to `_131_'. |
| renaming `$abc$436$g064' to `_132_'. |
| renaming `$abc$436$g065' to `_133_'. |
| renaming `$abc$436$g066' to `_134_'. |
| renaming `$abc$436$g067' to `_135_'. |
| renaming `$abc$436$g068' to `_136_'. |
| renaming `$abc$436$g069' to `_137_'. |
| renaming `$abc$436$g070' to `_138_'. |
| renaming `$abc$436$g071' to `_139_'. |
| renaming `$abc$436$g072' to `_140_'. |
| renaming `$abc$436$g073' to `_141_'. |
| renaming `$abc$436$g074' to `_142_'. |
| renaming `$abc$436$g075' to `_143_'. |
| renaming `$abc$436$g076' to `_144_'. |
| renaming `$abc$436$g077' to `_145_'. |
| renaming `$abc$436$g078' to `_146_'. |
| renaming `$abc$436$g079' to `_147_'. |
| renaming `$abc$436$g080' to `_148_'. |
| renaming `$abc$436$g081' to `_149_'. |
| renaming `$abc$436$g082' to `_150_'. |
| renaming `$abc$436$g083' to `_151_'. |
| renaming `$abc$436$g084' to `_152_'. |
| renaming `$abc$436$g085' to `_153_'. |
| renaming `$abc$436$g086' to `_154_'. |
| renaming `$abc$436$g087' to `_155_'. |
| renaming `$abc$436$g088' to `_156_'. |
| renaming `$abc$436$g089' to `_157_'. |
| renaming `$abc$436$g090' to `_158_'. |
| renaming `$abc$436$g091' to `_159_'. |
| renaming `$abc$436$g092' to `_160_'. |
| renaming `$abc$436$g093' to `_161_'. |
| renaming `$abc$436$g094' to `_162_'. |
| renaming `$abc$436$g095' to `_163_'. |
| renaming `$abc$436$g096' to `_164_'. |
| renaming `$abc$436$g097' to `_165_'. |
| renaming `$abc$436$g098' to `_166_'. |
| renaming `$abc$436$g099' to `_167_'. |
| renaming `$abc$436$g100' to `_168_'. |
| renaming `$abc$436$g101' to `_169_'. |
| renaming `$abc$436$g102' to `_170_'. |
| renaming `$abc$436$g103' to `_171_'. |
| renaming `$abc$436$g104' to `_172_'. |
| renaming `$abc$436$g105' to `_173_'. |
| renaming `$abc$436$g106' to `_174_'. |
| renaming `$abc$436$g107' to `_175_'. |
| renaming `$abc$436$n100_1' to `_003_'. |
| renaming `$abc$436$n101_1' to `_004_'. |
| renaming `$abc$436$n104_1' to `_005_'. |
| renaming `$abc$436$n105_1' to `_006_'. |
| renaming `$abc$436$n107_1' to `_007_'. |
| renaming `$abc$436$n108_1' to `_008_'. |
| renaming `$abc$436$n110_1' to `_009_'. |
| renaming `$abc$436$n111_1' to `_010_'. |
| renaming `$abc$436$n113_1' to `_011_'. |
| renaming `$abc$436$n114_1' to `_012_'. |
| renaming `$abc$436$n116_1' to `_013_'. |
| renaming `$abc$436$n117_1' to `_014_'. |
| renaming `$abc$436$n119_1' to `_015_'. |
| renaming `$abc$436$n120_1' to `_016_'. |
| renaming `$abc$436$n122_1' to `_017_'. |
| renaming `$abc$436$n123_1' to `_018_'. |
| renaming `$abc$436$n125' to `_019_'. |
| renaming `$abc$436$n126' to `_020_'. |
| renaming `$abc$436$n128' to `_021_'. |
| renaming `$abc$436$n129_1' to `_022_'. |
| renaming `$abc$436$n130_1' to `_023_'. |
| renaming `$abc$436$n131' to `_024_'. |
| renaming `$abc$436$n132' to `_025_'. |
| renaming `$abc$436$n134_1' to `_026_'. |
| renaming `$abc$436$n136_1' to `_027_'. |
| renaming `$abc$436$n138_1' to `_028_'. |
| renaming `$abc$436$n140_1' to `_029_'. |
| renaming `$abc$436$n142' to `_030_'. |
| renaming `$abc$436$n144' to `_031_'. |
| renaming `$abc$436$n146' to `_032_'. |
| renaming `$abc$436$n148_1' to `_033_'. |
| renaming `$abc$436$n149_1' to `_034_'. |
| renaming `$abc$436$n158' to `_035_'. |
| renaming `$abc$436$n159' to `_036_'. |
| renaming `$abc$436$n160' to `_037_'. |
| renaming `$abc$436$n169' to `_038_'. |
| renaming `$abc$436$n178' to `_039_'. |
| renaming `$abc$436$n179' to `_040_'. |
| renaming `$abc$436$n181' to `_041_'. |
| renaming `$abc$436$n182' to `_042_'. |
| renaming `$abc$436$n183' to `_043_'. |
| renaming `$abc$436$n185' to `_044_'. |
| renaming `$abc$436$n186' to `_045_'. |
| renaming `$abc$436$n187' to `_046_'. |
| renaming `$abc$436$n188' to `_047_'. |
| renaming `$abc$436$n189' to `_048_'. |
| renaming `$abc$436$n190' to `_049_'. |
| renaming `$abc$436$n191' to `_050_'. |
| renaming `$abc$436$n192' to `_051_'. |
| renaming `$abc$436$n193' to `_052_'. |
| renaming `$abc$436$n194' to `_053_'. |
| renaming `$abc$436$n195' to `_054_'. |
| renaming `$abc$436$n196' to `_055_'. |
| renaming `$abc$436$n197' to `_056_'. |
| renaming `$abc$436$n198' to `_057_'. |
| renaming `$abc$436$n200' to `_058_'. |
| renaming `$abc$436$n202' to `_059_'. |
| renaming `$abc$436$n96' to `_060_'. |
| renaming `$abc$436$n97_1' to `_061_'. |
| renaming `$abc$436$n98' to `_062_'. |
| renaming `$abc$436$n99_1' to `_063_'. |
| renaming `$memory$mem$\mem$350$wrmux[0][0]$372.Y' to `_064_'. |
| renaming `$memory$mem$\mem$350$wrmux[1][0]$378.Y' to `_065_'. |
| renaming `$memory$mem$\mem$350$wrmux[2][0]$384.Y' to `_066_'. |
| renaming `$memory$mem$\mem$350$wrmux[3][0]$390.Y' to `_067_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[0].ff' to `_176_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[1].ff' to `_177_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[2].ff' to `_178_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[3].ff' to `_179_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[4].ff' to `_180_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[5].ff' to `_181_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[6].ff' to `_182_'. |
| renaming `$memory$mem$\mem$350[0]$351.V[7].ff' to `_183_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[0].ff' to `_184_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[1].ff' to `_185_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[2].ff' to `_186_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[3].ff' to `_187_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[4].ff' to `_188_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[5].ff' to `_189_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[6].ff' to `_190_'. |
| renaming `$memory$mem$\mem$350[1]$353.V[7].ff' to `_191_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[0].ff' to `_192_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[1].ff' to `_193_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[2].ff' to `_194_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[3].ff' to `_195_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[4].ff' to `_196_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[5].ff' to `_197_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[6].ff' to `_198_'. |
| renaming `$memory$mem$\mem$350[2]$355.V[7].ff' to `_199_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[0].ff' to `_200_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[1].ff' to `_201_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[2].ff' to `_202_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[3].ff' to `_203_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[4].ff' to `_204_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[5].ff' to `_205_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[6].ff' to `_206_'. |
| renaming `$memory$mem$\mem$350[3]$357.V[7].ff' to `_207_'. |
| renaming `$procdff$321.V[0].P.PN.PN0.ff' to `_208_'. |
| renaming `$procdff$321.V[1].P.PN.PN0.ff' to `_209_'. |
| renaming `$procdff$325.V[0].ff' to `_210_'. |
| renaming `$procdff$326.V[0].P.PN.PN0.ff' to `_211_'. |
| renaming `$procdff$326.V[1].P.PN.PN0.ff' to `_212_'. |
| Dumping module `\sasc_top'. |
| renaming `$0\change[0:0]' to `_000_'. |
| renaming `$0\dpll_state[1:0]' to `_001_'. |
| renaming `$0\hold_reg[9:0]' to `_002_'. |
| renaming `$0\load[0:0]' to `_003_'. |
| renaming `$0\rx_bit_cnt[3:0]' to `_004_'. |
| renaming `$0\rx_go[0:0]' to `_005_'. |
| renaming `$0\rx_sio_ce[0:0]' to `_006_'. |
| renaming `$0\rx_valid[0:0]' to `_007_'. |
| renaming `$0\rxr[9:0]' to `_008_'. |
| renaming `$0\shift_en[0:0]' to `_009_'. |
| renaming `$0\shift_en_r[0:0]' to `_010_'. |
| renaming `$0\tx_bit_cnt[3:0]' to `_011_'. |
| renaming `$0\txd_o[0:0]' to `_012_'. |
| renaming `$0\txf_empty_r[0:0]' to `_013_'. |
| renaming `$abc$437$g000' to `_100_'. |
| renaming `$abc$437$g001' to `_101_'. |
| renaming `$abc$437$g002' to `_102_'. |
| renaming `$abc$437$g003' to `_103_'. |
| renaming `$abc$437$g004' to `_104_'. |
| renaming `$abc$437$g005' to `_105_'. |
| renaming `$abc$437$g006' to `_106_'. |
| renaming `$abc$437$g007' to `_107_'. |
| renaming `$abc$437$g008' to `_108_'. |
| renaming `$abc$437$g009' to `_109_'. |
| renaming `$abc$437$g010' to `_110_'. |
| renaming `$abc$437$g011' to `_111_'. |
| renaming `$abc$437$g012' to `_112_'. |
| renaming `$abc$437$g013' to `_113_'. |
| renaming `$abc$437$g014' to `_114_'. |
| renaming `$abc$437$g015' to `_115_'. |
| renaming `$abc$437$g016' to `_116_'. |
| renaming `$abc$437$g017' to `_117_'. |
| renaming `$abc$437$g018' to `_118_'. |
| renaming `$abc$437$g019' to `_119_'. |
| renaming `$abc$437$g020' to `_120_'. |
| renaming `$abc$437$g021' to `_121_'. |
| renaming `$abc$437$g022' to `_122_'. |
| renaming `$abc$437$g023' to `_123_'. |
| renaming `$abc$437$g024' to `_124_'. |
| renaming `$abc$437$g025' to `_125_'. |
| renaming `$abc$437$g026' to `_126_'. |
| renaming `$abc$437$g027' to `_127_'. |
| renaming `$abc$437$g028' to `_128_'. |
| renaming `$abc$437$g029' to `_129_'. |
| renaming `$abc$437$g030' to `_130_'. |
| renaming `$abc$437$g031' to `_131_'. |
| renaming `$abc$437$g032' to `_132_'. |
| renaming `$abc$437$g033' to `_133_'. |
| renaming `$abc$437$g034' to `_134_'. |
| renaming `$abc$437$g035' to `_135_'. |
| renaming `$abc$437$g036' to `_136_'. |
| renaming `$abc$437$g037' to `_137_'. |
| renaming `$abc$437$g038' to `_138_'. |
| renaming `$abc$437$g039' to `_139_'. |
| renaming `$abc$437$g040' to `_140_'. |
| renaming `$abc$437$g041' to `_141_'. |
| renaming `$abc$437$g042' to `_142_'. |
| renaming `$abc$437$g043' to `_143_'. |
| renaming `$abc$437$g044' to `_144_'. |
| renaming `$abc$437$g045' to `_145_'. |
| renaming `$abc$437$g046' to `_146_'. |
| renaming `$abc$437$g047' to `_147_'. |
| renaming `$abc$437$g048' to `_148_'. |
| renaming `$abc$437$g049' to `_149_'. |
| renaming `$abc$437$g050' to `_150_'. |
| renaming `$abc$437$g051' to `_151_'. |
| renaming `$abc$437$g052' to `_152_'. |
| renaming `$abc$437$g053' to `_153_'. |
| renaming `$abc$437$g054' to `_154_'. |
| renaming `$abc$437$g055' to `_155_'. |
| renaming `$abc$437$g056' to `_156_'. |
| renaming `$abc$437$g057' to `_157_'. |
| renaming `$abc$437$g058' to `_158_'. |
| renaming `$abc$437$g059' to `_159_'. |
| renaming `$abc$437$g060' to `_160_'. |
| renaming `$abc$437$g061' to `_161_'. |
| renaming `$abc$437$g062' to `_162_'. |
| renaming `$abc$437$g063' to `_163_'. |
| renaming `$abc$437$g064' to `_164_'. |
| renaming `$abc$437$g065' to `_165_'. |
| renaming `$abc$437$g066' to `_166_'. |
| renaming `$abc$437$g067' to `_167_'. |
| renaming `$abc$437$g068' to `_168_'. |
| renaming `$abc$437$g069' to `_169_'. |
| renaming `$abc$437$g070' to `_170_'. |
| renaming `$abc$437$g071' to `_171_'. |
| renaming `$abc$437$g072' to `_172_'. |
| renaming `$abc$437$g073' to `_173_'. |
| renaming `$abc$437$g074' to `_174_'. |
| renaming `$abc$437$g075' to `_175_'. |
| renaming `$abc$437$g076' to `_176_'. |
| renaming `$abc$437$g077' to `_177_'. |
| renaming `$abc$437$g078' to `_178_'. |
| renaming `$abc$437$g079' to `_179_'. |
| renaming `$abc$437$g080' to `_180_'. |
| renaming `$abc$437$g081' to `_181_'. |
| renaming `$abc$437$g082' to `_182_'. |
| renaming `$abc$437$g083' to `_183_'. |
| renaming `$abc$437$g084' to `_184_'. |
| renaming `$abc$437$g085' to `_185_'. |
| renaming `$abc$437$g086' to `_186_'. |
| renaming `$abc$437$g087' to `_187_'. |
| renaming `$abc$437$g088' to `_188_'. |
| renaming `$abc$437$g089' to `_189_'. |
| renaming `$abc$437$g090' to `_190_'. |
| renaming `$abc$437$g091' to `_191_'. |
| renaming `$abc$437$g092' to `_192_'. |
| renaming `$abc$437$g093' to `_193_'. |
| renaming `$abc$437$g094' to `_194_'. |
| renaming `$abc$437$g095' to `_195_'. |
| renaming `$abc$437$g096' to `_196_'. |
| renaming `$abc$437$g097' to `_197_'. |
| renaming `$abc$437$g098' to `_198_'. |
| renaming `$abc$437$g099' to `_199_'. |
| renaming `$abc$437$g100' to `_200_'. |
| renaming `$abc$437$g101' to `_201_'. |
| renaming `$abc$437$g102' to `_202_'. |
| renaming `$abc$437$g103' to `_203_'. |
| renaming `$abc$437$g104' to `_204_'. |
| renaming `$abc$437$g105' to `_205_'. |
| renaming `$abc$437$g106' to `_206_'. |
| renaming `$abc$437$g107' to `_207_'. |
| renaming `$abc$437$g108' to `_208_'. |
| renaming `$abc$437$g109' to `_209_'. |
| renaming `$abc$437$g110' to `_210_'. |
| renaming `$abc$437$g111' to `_211_'. |
| renaming `$abc$437$g112' to `_212_'. |
| renaming `$abc$437$g113' to `_213_'. |
| renaming `$abc$437$g114' to `_214_'. |
| renaming `$abc$437$g115' to `_215_'. |
| renaming `$abc$437$g116' to `_216_'. |
| renaming `$abc$437$g117' to `_217_'. |
| renaming `$abc$437$g118' to `_218_'. |
| renaming `$abc$437$g119' to `_219_'. |
| renaming `$abc$437$g120' to `_220_'. |
| renaming `$abc$437$g121' to `_221_'. |
| renaming `$abc$437$g122' to `_222_'. |
| renaming `$abc$437$g123' to `_223_'. |
| renaming `$abc$437$g124' to `_224_'. |
| renaming `$abc$437$g125' to `_225_'. |
| renaming `$abc$437$n102_1' to `_014_'. |
| renaming `$abc$437$n103' to `_015_'. |
| renaming `$abc$437$n104' to `_016_'. |
| renaming `$abc$437$n106' to `_017_'. |
| renaming `$abc$437$n108' to `_018_'. |
| renaming `$abc$437$n109' to `_019_'. |
| renaming `$abc$437$n111_1' to `_020_'. |
| renaming `$abc$437$n112_1' to `_021_'. |
| renaming `$abc$437$n113_1' to `_022_'. |
| renaming `$abc$437$n115' to `_023_'. |
| renaming `$abc$437$n117' to `_024_'. |
| renaming `$abc$437$n119' to `_025_'. |
| renaming `$abc$437$n121' to `_026_'. |
| renaming `$abc$437$n123' to `_027_'. |
| renaming `$abc$437$n125_1' to `_028_'. |
| renaming `$abc$437$n127_1' to `_029_'. |
| renaming `$abc$437$n129_1' to `_030_'. |
| renaming `$abc$437$n131_1' to `_031_'. |
| renaming `$abc$437$n133_1' to `_032_'. |
| renaming `$abc$437$n134_1' to `_033_'. |
| renaming `$abc$437$n135_1' to `_034_'. |
| renaming `$abc$437$n136_1' to `_035_'. |
| renaming `$abc$437$n138_1' to `_036_'. |
| renaming `$abc$437$n139_1' to `_037_'. |
| renaming `$abc$437$n140_1' to `_038_'. |
| renaming `$abc$437$n142_1' to `_039_'. |
| renaming `$abc$437$n143_1' to `_040_'. |
| renaming `$abc$437$n145_1' to `_041_'. |
| renaming `$abc$437$n146_1' to `_042_'. |
| renaming `$abc$437$n147' to `_043_'. |
| renaming `$abc$437$n148' to `_044_'. |
| renaming `$abc$437$n150_1' to `_045_'. |
| renaming `$abc$437$n151' to `_046_'. |
| renaming `$abc$437$n152_1' to `_047_'. |
| renaming `$abc$437$n153_1' to `_048_'. |
| renaming `$abc$437$n155_1' to `_049_'. |
| renaming `$abc$437$n157' to `_050_'. |
| renaming `$abc$437$n158_1' to `_051_'. |
| renaming `$abc$437$n159' to `_052_'. |
| renaming `$abc$437$n160' to `_053_'. |
| renaming `$abc$437$n161' to `_054_'. |
| renaming `$abc$437$n162_1' to `_055_'. |
| renaming `$abc$437$n164' to `_056_'. |
| renaming `$abc$437$n165' to `_057_'. |
| renaming `$abc$437$n166' to `_058_'. |
| renaming `$abc$437$n168' to `_059_'. |
| renaming `$abc$437$n169_1' to `_060_'. |
| renaming `$abc$437$n170' to `_061_'. |
| renaming `$abc$437$n171' to `_062_'. |
| renaming `$abc$437$n173_1' to `_063_'. |
| renaming `$abc$437$n174' to `_064_'. |
| renaming `$abc$437$n175' to `_065_'. |
| renaming `$abc$437$n176' to `_066_'. |
| renaming `$abc$437$n186' to `_067_'. |
| renaming `$abc$437$n187' to `_068_'. |
| renaming `$abc$437$n188' to `_069_'. |
| renaming `$abc$437$n189' to `_070_'. |
| renaming `$abc$437$n191' to `_071_'. |
| renaming `$abc$437$n192' to `_072_'. |
| renaming `$abc$437$n193' to `_073_'. |
| renaming `$abc$437$n194' to `_074_'. |
| renaming `$abc$437$n195' to `_075_'. |
| renaming `$abc$437$n196' to `_076_'. |
| renaming `$abc$437$n198' to `_077_'. |
| renaming `$abc$437$n199' to `_078_'. |
| renaming `$abc$437$n200' to `_079_'. |
| renaming `$abc$437$n201' to `_080_'. |
| renaming `$abc$437$n202' to `_081_'. |
| renaming `$abc$437$n203' to `_082_'. |
| renaming `$abc$437$n205' to `_083_'. |
| renaming `$abc$437$n206' to `_084_'. |
| renaming `$abc$437$n207' to `_085_'. |
| renaming `$abc$437$n209' to `_086_'. |
| renaming `$abc$437$n210' to `_087_'. |
| renaming `$abc$437$n211' to `_088_'. |
| renaming `$abc$437$n212' to `_089_'. |
| renaming `$abc$437$n214' to `_090_'. |
| renaming `$abc$437$n215' to `_091_'. |
| renaming `$abc$437$n216' to `_092_'. |
| renaming `$abc$437$n217' to `_093_'. |
| renaming `$abc$437$n219' to `_094_'. |
| renaming `$abc$437$n220' to `_095_'. |
| renaming `$abc$437$n96_1' to `_096_'. |
| renaming `$abc$437$n97_1' to `_097_'. |
| renaming `$abc$437$n98_1' to `_098_'. |
| renaming `$abc$437$n99' to `_099_'. |
| renaming `$procdff$327.V[0].ff' to `_226_'. |
| renaming `$procdff$328.V[0].ff' to `_227_'. |
| renaming `$procdff$330.V[0].ff' to `_228_'. |
| renaming `$procdff$330.V[1].ff' to `_229_'. |
| renaming `$procdff$330.V[2].ff' to `_230_'. |
| renaming `$procdff$330.V[3].ff' to `_231_'. |
| renaming `$procdff$330.V[4].ff' to `_232_'. |
| renaming `$procdff$330.V[5].ff' to `_233_'. |
| renaming `$procdff$330.V[6].ff' to `_234_'. |
| renaming `$procdff$330.V[7].ff' to `_235_'. |
| renaming `$procdff$330.V[8].ff' to `_236_'. |
| renaming `$procdff$330.V[9].ff' to `_237_'. |
| renaming `$procdff$331.V[0].ff' to `_238_'. |
| renaming `$procdff$332.V[0].ff' to `_239_'. |
| renaming `$procdff$332.V[1].ff' to `_240_'. |
| renaming `$procdff$332.V[2].ff' to `_241_'. |
| renaming `$procdff$332.V[3].ff' to `_242_'. |
| renaming `$procdff$333.V[0].ff' to `_243_'. |
| renaming `$procdff$334.V[0].ff' to `_244_'. |
| renaming `$procdff$335.V[0].ff' to `_245_'. |
| renaming `$procdff$336.V[0].ff' to `_246_'. |
| renaming `$procdff$337.V[0].ff' to `_247_'. |
| renaming `$procdff$337.V[1].ff' to `_248_'. |
| renaming `$procdff$337.V[2].ff' to `_249_'. |
| renaming `$procdff$337.V[3].ff' to `_250_'. |
| renaming `$procdff$338.V[0].ff' to `_251_'. |
| renaming `$procdff$339.V[0].ff' to `_252_'. |
| renaming `$procdff$340.V[0].ff' to `_253_'. |
| renaming `$procdff$341.V[2].ff' to `_254_'. |
| renaming `$procdff$341.V[3].ff' to `_255_'. |
| renaming `$procdff$341.V[4].ff' to `_256_'. |
| renaming `$procdff$341.V[5].ff' to `_257_'. |
| renaming `$procdff$341.V[6].ff' to `_258_'. |
| renaming `$procdff$341.V[7].ff' to `_259_'. |
| renaming `$procdff$341.V[8].ff' to `_260_'. |
| renaming `$procdff$341.V[9].ff' to `_261_'. |
| renaming `$procdff$342.V[0].ff' to `_262_'. |
| renaming `$procdff$345.V[0].ff' to `_263_'. |
| renaming `$procdff$346.V[0].P.PN.PN1.ff' to `_264_'. |
| renaming `$procdff$346.V[1].P.PN.PN0.ff' to `_265_'. |
| renaming `$procdff$347.V[0].ff' to `_266_'. |
| renaming `$procdff$348.V[0].ff' to `_267_'. |
| renaming `$procdff$349.V[0].ff' to `_268_'. |
| |
| READY. |
