| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [ERROR:PP0101] rtl/fifo4.v:57 Cannot open include file "timescale.v". |
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| [ERROR:PP0101] rtl/simple_spi_top.v:74 Cannot open include file "timescale.v". |
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| [WARNI:PA0205] cache/synth.v:1 No timescale set for "$paramod\fifo4\dw=8". |
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| [WARNI:PA0205] cache/synth.v:282 No timescale set for "simple_spi_top". |
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| [WARNI:PA0205] timescale.v:5 No timescale set for "fifo4". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@$paramod\fifo4\dw=8". |
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| [INFO :CP0303] timescale.v:5 Compile module "work@fifo4". |
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| [INFO :CP0303] cache/synth.v:282 Compile module "work@simple_spi_top". |
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| [NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "dout", |
| there are 2 more instances of this message. |
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| [NOTE :CP0309] timescale.v:5 Implicit port type (wire) for "dout", |
| there are 2 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] cache/synth.v:1 Top level module "work@$paramod\fifo4\dw=8". |
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| [NOTE :EL0503] cache/synth.v:282 Top level module "work@simple_spi_top". |
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| [WARNI:EL0505] timescale.v:3 Multiply defined module "work@simple_spi_top", |
| cache/synth.v:282 previous definition. |
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| [NOTE :EL0504] Multiple top level modules in design. |
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| [WARNI:EL0500] cache/synth.v:1191 Cannot find a module definition for "work@simple_spi_top::$paramod\fifo4\dw=8 ". |
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| [WARNI:EL0500] cache/synth.v:1202 Cannot find a module definition for "work@simple_spi_top::$paramod\fifo4\dw=8 ". |
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| [NOTE :EL0508] Nb Top level modules: 2. |
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| [NOTE :EL0509] Max instance depth: 2. |
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| [NOTE :EL0510] Nb instances: 4. |
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| [NOTE :EL0511] Nb leaf instances: 3. |
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| [WARNI:EL0512] Nb undefined modules: 1. |
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| [WARNI:EL0513] Nb undefined instances: 2. |
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| [ FATAL] : 0 |
| [ ERROR] : 2 |
| [WARNING] : 8 |
| [ NOTE] : 9 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
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| 2.04user 0.02system 0:02.08elapsed 99%CPU (0avgtext+0avgdata 65700maxresident)k |
| 104inputs+112outputs (0major+13755minor)pagefaults 0swaps |
