| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [ERROR:PP0101] rtl/spi_clgen.v:41 Cannot open include file "spi_defines.v". |
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| [ERROR:PP0101] rtl/spi_clgen.v:42 Cannot open include file "timescale.v". |
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| [ERROR:PP0102] rtl/spi_clgen.v:53 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_clgen.v:62 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_clgen.v:67 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_clgen.v:68 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_clgen.v:74 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_clgen.v:80 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0101] rtl/spi_shift.v:41 Cannot open include file "spi_defines.v". |
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| [ERROR:PP0101] rtl/spi_shift.v:42 Cannot open include file "timescale.v". |
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| [ERROR:PP0102] rtl/spi_shift.v:55 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:65 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PP0102] rtl/spi_shift.v:73 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:74 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PP0102] rtl/spi_shift.v:75 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:76 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:82 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:83 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:84 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:95 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:99 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:101 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:122 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_shift.v:129 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PP0102] rtl/spi_shift.v:234 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0101] rtl/spi_top.v:42 Cannot open include file "spi_defines.v". |
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| [ERROR:PP0101] rtl/spi_top.v:43 Cannot open include file "timescale.v". |
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| [ERROR:PP0102] rtl/spi_top.v:72 Unknown macro "SPI_SS_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:82 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_top.v:83 Unknown macro "SPI_CTRL_BIT_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:84 Unknown macro "SPI_SS_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:86 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PP0102] rtl/spi_top.v:89 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:104 Unknown macro "SPI_DEVIDE". |
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| [ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:105 Unknown macro "SPI_CTRL". |
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| [ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:106 Unknown macro "SPI_TX_0". |
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| [ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:107 Unknown macro "SPI_TX_1". |
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| [ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:108 Unknown macro "SPI_TX_2". |
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| [ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:109 Unknown macro "SPI_TX_3". |
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| [ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:110 Unknown macro "SPI_SS". |
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| [ERROR:PP0102] rtl/spi_top.v:115 Unknown macro "SPI_OFS_BITS". |
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| [ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_RX_0". |
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| [ERROR:PP0102] rtl/spi_top.v:128 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PP0102] rtl/spi_top.v:129 Unknown macro "SPI_RX_1". |
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| [ERROR:PP0102] rtl/spi_top.v:130 Unknown macro "SPI_RX_2". |
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| [ERROR:PP0102] rtl/spi_top.v:131 Unknown macro "SPI_RX_3". |
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| [ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL". |
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| [ERROR:PP0102] rtl/spi_top.v:134 Unknown macro "SPI_CTRL_BIT_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DEVIDE". |
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| [ERROR:PP0102] rtl/spi_top.v:135 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS". |
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| [ERROR:PP0102] rtl/spi_top.v:136 Unknown macro "SPI_SS_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:177 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PP0102] rtl/spi_top.v:215 Unknown macro "SPI_CTRL_BIT_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:221 Unknown macro "SPI_CTRL_BIT_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:224 Unknown macro "SPI_CTRL_GO". |
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| [ERROR:PP0102] rtl/spi_top.v:227 Unknown macro "SPI_CTRL_RX_NEGEDGE". |
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| [ERROR:PP0102] rtl/spi_top.v:228 Unknown macro "SPI_CTRL_TX_NEGEDGE". |
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| [ERROR:PP0102] rtl/spi_top.v:229 Unknown macro "SPI_CTRL_GO". |
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| [ERROR:PP0102] rtl/spi_top.v:230 Unknown macro "SPI_CTRL_CHAR_LEN". |
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| [ERROR:PP0102] rtl/spi_top.v:231 Unknown macro "SPI_CTRL_LSB". |
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| [ERROR:PP0102] rtl/spi_top.v:232 Unknown macro "SPI_CTRL_IE". |
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| [ERROR:PP0102] rtl/spi_top.v:233 Unknown macro "SPI_CTRL_ASS". |
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| [ERROR:PP0102] rtl/spi_top.v:239 Unknown macro "SPI_SS_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:273 Unknown macro "SPI_SS_NB". |
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| [ERROR:PP0102] rtl/spi_top.v:279 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0207] rtl/spi_clgen.v:51 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!!', |
| input [SURELOG_MACRO_NOT_DEFINED:SPI_DIVIDER_LEN!!! -1:0] divider; // clock divider (output clock is divided by this value) |
| ^-- ./slpp_unit/work/rtl/spi_clgen.v:51 col:13. |
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| [ERROR:PA0203] rtl/spi_clgen.v:51 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0203] rtl/spi_clgen.v:65 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0203] rtl/spi_clgen.v:66 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0203] rtl/spi_clgen.v:72 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0203] rtl/spi_clgen.v:78 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0207] timescale.v:13 Syntax error: no viable alternative at input 'input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!!', |
| input [SURELOG_MACRO_NOT_DEFINED:SPI_CHAR_LEN_BITS!!! -1:0] len; // data len in bits (minus one) |
| ^-- ./slpp_unit/work/rtl/spi_shift.v:53 col:9. |
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| [ERROR:PA0203] timescale.v:13 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:40 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:41 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:42 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:53 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:57 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:59 Unknown macro "SPI_CHAR_LEN_BITS". |
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| [ERROR:PA0203] timescale.v:87 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PA0207] timescale.v:29 Syntax error: no viable alternative at input 'output [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!!', |
| output [SURELOG_MACRO_NOT_DEFINED:SPI_SS_NB!!! -1:0] ss_pad_o; // slave select |
| ^-- ./slpp_unit/work/rtl/spi_top.v:70 col:19. |
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| [ERROR:PA0203] timescale.v:29 Unknown macro "SPI_SS_NB". |
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| [ERROR:PA0203] timescale.v:61 Unknown macro "SPI_DEVIDE". |
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| [ERROR:PA0203] timescale.v:62 Unknown macro "SPI_CTRL". |
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| [ERROR:PA0203] timescale.v:63 Unknown macro "SPI_TX_0". |
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| [ERROR:PA0203] timescale.v:64 Unknown macro "SPI_TX_1". |
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| [ERROR:PA0203] timescale.v:65 Unknown macro "SPI_TX_2". |
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| [ERROR:PA0203] timescale.v:66 Unknown macro "SPI_TX_3". |
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| [ERROR:PA0203] timescale.v:67 Unknown macro "SPI_SS". |
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| [ERROR:PA0203] timescale.v:73 Unknown macro "SPI_RX_0". |
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| [ERROR:PA0203] timescale.v:73 Unknown macro "SPI_MAX_CHAR". |
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| [ERROR:PA0203] timescale.v:74 Unknown macro "SPI_RX_1". |
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| [ERROR:PA0203] timescale.v:75 Unknown macro "SPI_RX_2". |
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| [ERROR:PA0203] timescale.v:76 Unknown macro "SPI_RX_3". |
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| [ERROR:PA0203] timescale.v:77 Unknown macro "SPI_CTRL". |
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| [ERROR:PA0203] timescale.v:78 Unknown macro "SPI_DEVIDE". |
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| [ERROR:PA0203] timescale.v:79 Unknown macro "SPI_SS". |
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| [ERROR:PA0203] timescale.v:120 Unknown macro "SPI_DIVIDER_LEN". |
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| [ERROR:PA0203] timescale.v:130 Unknown macro "SPI_CTRL_BIT_NB". |
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| [ERROR:PA0203] timescale.v:154 Unknown macro "SPI_SS_NB". |
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| [ERROR:PA0203] timescale.v:160 Unknown macro "SPI_SS_NB". |
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| [WARNI:PA0205] cache/synth.v:1 No timescale set for "spi_clgen". |
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| [WARNI:PA0205] cache/synth.v:359 No timescale set for "spi_shift". |
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| [WARNI:PA0205] cache/synth.v:4166 No timescale set for "spi_top". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] cache/synth.v:1 Compile module "work@spi_clgen". |
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| [INFO :CP0303] cache/synth.v:359 Compile module "work@spi_shift". |
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| [INFO :CP0303] cache/synth.v:4166 Compile module "work@spi_top". |
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| [NOTE :CP0309] cache/synth.v:359 Implicit port type (wire) for "last", |
| there are 1 more instances of this message. |
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| [NOTE :CP0309] cache/synth.v:4166 Implicit port type (wire) for "wb_err_o", |
| there are 3 more instances of this message. |
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| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] cache/synth.v:4166 Top level module "work@spi_top". |
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| [WARNI:EL0505] rtl/spi_clgen.v:42 Multiply defined module "work@spi_clgen", |
| cache/synth.v:1 previous definition. |
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| [WARNI:EL0505] timescale.v:2 Multiply defined module "work@spi_shift", |
| cache/synth.v:359 previous definition. |
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| [WARNI:EL0505] timescale.v:2 Multiply defined module "work@spi_top", |
| cache/synth.v:4166 previous definition. |
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| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 2. |
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| [NOTE :EL0510] Nb instances: 3. |
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| [NOTE :EL0511] Nb leaf instances: 2. |
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| [ FATAL] : 0 |
| [ ERROR] : 109 |
| [WARNING] : 6 |
| [ NOTE] : 7 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 3.96user 0.10system 0:04.26elapsed 95%CPU (0avgtext+0avgdata 116516maxresident)k |
| 392inputs+392outputs (0major+26454minor)pagefaults 0swaps |
