blob: dfac4573301bde6772c0217b13935d5f735dcc6a [file] [log] [blame] [edit]
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* SURELOG System Verilog Compiler/Linter *
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[INFO :CM0023] Creating log file ./slpp_unit/surelog.log.
[INFO :CM0024] Executing with 4 threads.
[INFO :CM0020] Separate compilation-unit mode is on.
[ERROR:PP0101] rtl/usb_phy.v:75 Cannot open include file "timescale.v".
[ERROR:PP0101] rtl/usb_rx_phy.v:77 Cannot open include file "timescale.v".
[ERROR:PP0101] rtl/usb_tx_phy.v:75 Cannot open include file "timescale.v".
[WARNI:PA0205] cache/synth.v:1 No timescale set for "usb_phy".
[WARNI:PA0205] cache/synth.v:109 No timescale set for "usb_rx_phy".
[WARNI:PA0205] cache/synth.v:645 No timescale set for "usb_tx_phy".
[INFO :CP0300] Compilation...
[INFO :CP0303] cache/synth.v:1 Compile module "work@usb_phy".
[INFO :CP0303] cache/synth.v:109 Compile module "work@usb_rx_phy".
[INFO :CP0303] cache/synth.v:645 Compile module "work@usb_tx_phy".
[NOTE :CP0309] cache/synth.v:1 Implicit port type (wire) for "txdp",
there are 8 more instances of this message.
[NOTE :CP0309] cache/synth.v:109 Implicit port type (wire) for "RxError_o".
[INFO :EL0526] Design Elaboration...
[NOTE :EL0503] cache/synth.v:1 Top level module "work@usb_phy".
[WARNI:EL0505] timescale.v:2 Multiply defined module "work@usb_phy",
cache/synth.v:1 previous definition.
[WARNI:EL0505] timescale.v:2 Multiply defined module "work@usb_rx_phy",
cache/synth.v:109 previous definition.
[WARNI:EL0505] timescale.v:2 Multiply defined module "work@usb_tx_phy",
cache/synth.v:645 previous definition.
[NOTE :EL0508] Nb Top level modules: 1.
[NOTE :EL0509] Max instance depth: 2.
[NOTE :EL0510] Nb instances: 3.
[NOTE :EL0511] Nb leaf instances: 2.
[ FATAL] : 0
[ ERROR] : 3
[WARNING] : 6
[ NOTE] : 7
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* End SURELOG SVerilog Compiler/Linter *
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1.87user 0.03system 0:01.93elapsed 98%CPU (0avgtext+0avgdata 65888maxresident)k
128inputs+136outputs (0major+13886minor)pagefaults 0swaps