SVIncCompil/Testcases/YosysTests/misc/insbuf/top.v - third_party/Surelog - Git at Google

 module top    (
 out,
 i,
 clk,
 o,
 in
 );
     output [7:0] out;
     input clk, in;
     reg [7:0] out;
     input i;
     output o;

     always @(posedge clk)
 	begin
 		out    <= out << 1;
 		out[0] <= in;
 	end

 endmodule
	module top (
	out,
	i,
	clk,
	o,
	in
	);
	output [7:0] out;
	input clk, in;
	reg [7:0] out;
	input i;
	output o;

	always @(posedge clk)
	begin
	out <= out << 1;
	out[0] <= in;
	end

	endmodule