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foss-fpga-tools
/
third_party
/
Surelog
/
refs/heads/mithro-patch-1
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
pmuxtree
/
top.v
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module
top
(
C
,
S
,
Y
);
input C
;
input
[
1
:
0
]
S
;
output reg
[
3
:
0
]
Y
;
initial Y
=
0
;
always
@(
posedge C
)
begin
case
(
S
)
2
'b00: Y <= 4'
b0001
;
2
'b01: Y <= 4'
b0010
;
2
'b10: Y <= 4'
b0100
;
2
'b11: Y <= 4'
b1000
;
endcase
end
endmodule