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foss-fpga-tools
/
third_party
/
Surelog
/
refs/heads/mithro-patch-1
/
.
/
SVIncCompil
/
Testcases
/
YosysTests
/
misc
/
scripts
/
rename.ys
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read_verilog
../
top
.
v
proc
tee
-
o result
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log rename middle mid_module
tee
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o result
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log
dump
