blob: 9be2bb443a399320c47b0b84726e4dfd13cbcb86 [file] [log] [blame] [edit]
read_verilog ../top.v
proc
clk2fflogic
tee -o result.log dump
synth -top top
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v